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525 lines
13 KiB
525 lines
13 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Driver for the Diolan DLN-2 USB-GPIO adapter |
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* |
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* Copyright (c) 2014 Intel Corporation |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/slab.h> |
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#include <linux/types.h> |
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#include <linux/irqdomain.h> |
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#include <linux/irq.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/platform_device.h> |
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#include <linux/mfd/dln2.h> |
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#define DLN2_GPIO_ID 0x01 |
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#define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID) |
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#define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID) |
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#define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID) |
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#define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID) |
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#define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID) |
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#define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID) |
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#define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID) |
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#define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID) |
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#define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID) |
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#define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID) |
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#define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID) |
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#define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID) |
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#define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID) |
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#define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID) |
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#define DLN2_GPIO_EVENT_NONE 0 |
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#define DLN2_GPIO_EVENT_CHANGE 1 |
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#define DLN2_GPIO_EVENT_LVL_HIGH 2 |
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#define DLN2_GPIO_EVENT_LVL_LOW 3 |
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#define DLN2_GPIO_EVENT_CHANGE_RISING 0x11 |
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#define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21 |
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#define DLN2_GPIO_EVENT_MASK 0x0F |
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#define DLN2_GPIO_MAX_PINS 32 |
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struct dln2_gpio { |
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struct platform_device *pdev; |
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struct gpio_chip gpio; |
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/* |
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* Cache pin direction to save us one transfer, since the hardware has |
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* separate commands to read the in and out values. |
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*/ |
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DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS); |
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/* active IRQs - not synced to hardware */ |
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DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS); |
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/* active IRQS - synced to hardware */ |
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DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS); |
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int irq_type[DLN2_GPIO_MAX_PINS]; |
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struct mutex irq_lock; |
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}; |
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struct dln2_gpio_pin { |
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__le16 pin; |
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}; |
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struct dln2_gpio_pin_val { |
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__le16 pin __packed; |
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u8 value; |
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}; |
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static int dln2_gpio_get_pin_count(struct platform_device *pdev) |
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{ |
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int ret; |
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__le16 count; |
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int len = sizeof(count); |
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ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len); |
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if (ret < 0) |
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return ret; |
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if (len < sizeof(count)) |
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return -EPROTO; |
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return le16_to_cpu(count); |
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} |
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static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin) |
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{ |
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struct dln2_gpio_pin req = { |
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.pin = cpu_to_le16(pin), |
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}; |
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return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req)); |
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} |
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static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin) |
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{ |
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int ret; |
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struct dln2_gpio_pin req = { |
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.pin = cpu_to_le16(pin), |
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}; |
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struct dln2_gpio_pin_val rsp; |
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int len = sizeof(rsp); |
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ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len); |
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if (ret < 0) |
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return ret; |
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if (len < sizeof(rsp) || req.pin != rsp.pin) |
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return -EPROTO; |
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return rsp.value; |
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} |
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static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin) |
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{ |
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int ret; |
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ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin); |
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if (ret < 0) |
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return ret; |
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return !!ret; |
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} |
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static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin) |
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{ |
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int ret; |
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ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin); |
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if (ret < 0) |
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return ret; |
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return !!ret; |
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} |
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static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2, |
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unsigned int pin, int value) |
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{ |
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struct dln2_gpio_pin_val req = { |
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.pin = cpu_to_le16(pin), |
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.value = value, |
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}; |
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return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req, |
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sizeof(req)); |
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} |
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#define DLN2_GPIO_DIRECTION_IN 0 |
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#define DLN2_GPIO_DIRECTION_OUT 1 |
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static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
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struct dln2_gpio_pin req = { |
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.pin = cpu_to_le16(offset), |
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}; |
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struct dln2_gpio_pin_val rsp; |
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int len = sizeof(rsp); |
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int ret; |
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ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset); |
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if (ret < 0) |
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return ret; |
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/* cache the pin direction */ |
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ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION, |
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&req, sizeof(req), &rsp, &len); |
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if (ret < 0) |
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return ret; |
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if (len < sizeof(rsp) || req.pin != rsp.pin) { |
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ret = -EPROTO; |
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goto out_disable; |
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} |
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switch (rsp.value) { |
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case DLN2_GPIO_DIRECTION_IN: |
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clear_bit(offset, dln2->output_enabled); |
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return 0; |
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case DLN2_GPIO_DIRECTION_OUT: |
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set_bit(offset, dln2->output_enabled); |
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return 0; |
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default: |
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ret = -EPROTO; |
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goto out_disable; |
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} |
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out_disable: |
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dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset); |
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return ret; |
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} |
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static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
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dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset); |
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} |
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static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset) |
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{ |
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struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
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if (test_bit(offset, dln2->output_enabled)) |
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return GPIO_LINE_DIRECTION_OUT; |
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return GPIO_LINE_DIRECTION_IN; |
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} |
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static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset) |
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{ |
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struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
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int dir; |
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dir = dln2_gpio_get_direction(chip, offset); |
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if (dir < 0) |
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return dir; |
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if (dir == GPIO_LINE_DIRECTION_IN) |
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return dln2_gpio_pin_get_in_val(dln2, offset); |
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return dln2_gpio_pin_get_out_val(dln2, offset); |
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} |
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static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
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{ |
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struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
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dln2_gpio_pin_set_out_val(dln2, offset, value); |
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} |
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static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset, |
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unsigned dir) |
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{ |
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struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
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struct dln2_gpio_pin_val req = { |
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.pin = cpu_to_le16(offset), |
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.value = dir, |
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}; |
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int ret; |
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ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION, |
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&req, sizeof(req)); |
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if (ret < 0) |
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return ret; |
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if (dir == DLN2_GPIO_DIRECTION_OUT) |
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set_bit(offset, dln2->output_enabled); |
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else |
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clear_bit(offset, dln2->output_enabled); |
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return ret; |
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} |
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static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
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{ |
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return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN); |
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} |
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static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset, |
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int value) |
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{ |
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struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
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int ret; |
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ret = dln2_gpio_pin_set_out_val(dln2, offset, value); |
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if (ret < 0) |
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return ret; |
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return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT); |
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} |
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static int dln2_gpio_set_config(struct gpio_chip *chip, unsigned offset, |
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unsigned long config) |
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{ |
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struct dln2_gpio *dln2 = gpiochip_get_data(chip); |
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__le32 duration; |
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if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) |
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return -ENOTSUPP; |
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duration = cpu_to_le32(pinconf_to_config_argument(config)); |
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return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE, |
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&duration, sizeof(duration)); |
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} |
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static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin, |
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unsigned type, unsigned period) |
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{ |
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struct { |
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__le16 pin; |
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u8 type; |
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__le16 period; |
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} __packed req = { |
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.pin = cpu_to_le16(pin), |
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.type = type, |
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.period = cpu_to_le16(period), |
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}; |
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return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG, |
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&req, sizeof(req)); |
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} |
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static void dln2_irq_unmask(struct irq_data *irqd) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); |
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struct dln2_gpio *dln2 = gpiochip_get_data(gc); |
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int pin = irqd_to_hwirq(irqd); |
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set_bit(pin, dln2->unmasked_irqs); |
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} |
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static void dln2_irq_mask(struct irq_data *irqd) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); |
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struct dln2_gpio *dln2 = gpiochip_get_data(gc); |
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int pin = irqd_to_hwirq(irqd); |
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clear_bit(pin, dln2->unmasked_irqs); |
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} |
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static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); |
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struct dln2_gpio *dln2 = gpiochip_get_data(gc); |
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int pin = irqd_to_hwirq(irqd); |
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switch (type) { |
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case IRQ_TYPE_LEVEL_HIGH: |
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dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH; |
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break; |
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case IRQ_TYPE_LEVEL_LOW: |
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dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW; |
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break; |
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case IRQ_TYPE_EDGE_BOTH: |
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dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE; |
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break; |
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case IRQ_TYPE_EDGE_RISING: |
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dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING; |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING; |
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break; |
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default: |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static void dln2_irq_bus_lock(struct irq_data *irqd) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); |
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struct dln2_gpio *dln2 = gpiochip_get_data(gc); |
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mutex_lock(&dln2->irq_lock); |
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} |
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static void dln2_irq_bus_unlock(struct irq_data *irqd) |
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{ |
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struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); |
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struct dln2_gpio *dln2 = gpiochip_get_data(gc); |
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int pin = irqd_to_hwirq(irqd); |
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int enabled, unmasked; |
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unsigned type; |
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int ret; |
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enabled = test_bit(pin, dln2->enabled_irqs); |
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unmasked = test_bit(pin, dln2->unmasked_irqs); |
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if (enabled != unmasked) { |
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if (unmasked) { |
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type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK; |
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set_bit(pin, dln2->enabled_irqs); |
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} else { |
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type = DLN2_GPIO_EVENT_NONE; |
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clear_bit(pin, dln2->enabled_irqs); |
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} |
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ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0); |
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if (ret) |
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dev_err(dln2->gpio.parent, "failed to set event\n"); |
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} |
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mutex_unlock(&dln2->irq_lock); |
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} |
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static struct irq_chip dln2_gpio_irqchip = { |
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.name = "dln2-irq", |
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.irq_mask = dln2_irq_mask, |
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.irq_unmask = dln2_irq_unmask, |
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.irq_set_type = dln2_irq_set_type, |
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.irq_bus_lock = dln2_irq_bus_lock, |
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.irq_bus_sync_unlock = dln2_irq_bus_unlock, |
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}; |
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static void dln2_gpio_event(struct platform_device *pdev, u16 echo, |
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const void *data, int len) |
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{ |
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int pin, irq; |
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const struct { |
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__le16 count; |
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__u8 type; |
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__le16 pin; |
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__u8 value; |
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} __packed *event = data; |
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struct dln2_gpio *dln2 = platform_get_drvdata(pdev); |
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if (len < sizeof(*event)) { |
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dev_err(dln2->gpio.parent, "short event message\n"); |
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return; |
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} |
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pin = le16_to_cpu(event->pin); |
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if (pin >= dln2->gpio.ngpio) { |
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dev_err(dln2->gpio.parent, "out of bounds pin %d\n", pin); |
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return; |
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} |
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irq = irq_find_mapping(dln2->gpio.irq.domain, pin); |
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if (!irq) { |
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dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin); |
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return; |
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} |
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switch (dln2->irq_type[pin]) { |
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case DLN2_GPIO_EVENT_CHANGE_RISING: |
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if (event->value) |
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generic_handle_irq(irq); |
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break; |
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case DLN2_GPIO_EVENT_CHANGE_FALLING: |
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if (!event->value) |
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generic_handle_irq(irq); |
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break; |
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default: |
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generic_handle_irq(irq); |
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} |
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} |
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static int dln2_gpio_probe(struct platform_device *pdev) |
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{ |
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struct dln2_gpio *dln2; |
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struct device *dev = &pdev->dev; |
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struct gpio_irq_chip *girq; |
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int pins; |
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int ret; |
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pins = dln2_gpio_get_pin_count(pdev); |
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if (pins < 0) { |
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dev_err(dev, "failed to get pin count: %d\n", pins); |
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return pins; |
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} |
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if (pins > DLN2_GPIO_MAX_PINS) { |
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pins = DLN2_GPIO_MAX_PINS; |
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dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS); |
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} |
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dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL); |
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if (!dln2) |
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return -ENOMEM; |
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mutex_init(&dln2->irq_lock); |
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dln2->pdev = pdev; |
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dln2->gpio.label = "dln2"; |
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dln2->gpio.parent = dev; |
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dln2->gpio.owner = THIS_MODULE; |
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dln2->gpio.base = -1; |
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dln2->gpio.ngpio = pins; |
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dln2->gpio.can_sleep = true; |
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dln2->gpio.set = dln2_gpio_set; |
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dln2->gpio.get = dln2_gpio_get; |
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dln2->gpio.request = dln2_gpio_request; |
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dln2->gpio.free = dln2_gpio_free; |
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dln2->gpio.get_direction = dln2_gpio_get_direction; |
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dln2->gpio.direction_input = dln2_gpio_direction_input; |
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dln2->gpio.direction_output = dln2_gpio_direction_output; |
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dln2->gpio.set_config = dln2_gpio_set_config; |
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girq = &dln2->gpio.irq; |
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girq->chip = &dln2_gpio_irqchip; |
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/* The event comes from the outside so no parent handler */ |
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girq->parent_handler = NULL; |
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girq->num_parents = 0; |
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girq->parents = NULL; |
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girq->default_type = IRQ_TYPE_NONE; |
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girq->handler = handle_simple_irq; |
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platform_set_drvdata(pdev, dln2); |
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ret = devm_gpiochip_add_data(dev, &dln2->gpio, dln2); |
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if (ret < 0) { |
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dev_err(dev, "failed to add gpio chip: %d\n", ret); |
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return ret; |
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} |
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ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV, |
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dln2_gpio_event); |
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if (ret) { |
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dev_err(dev, "failed to register event cb: %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static int dln2_gpio_remove(struct platform_device *pdev) |
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{ |
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dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV); |
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return 0; |
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} |
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static struct platform_driver dln2_gpio_driver = { |
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.driver.name = "dln2-gpio", |
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.probe = dln2_gpio_probe, |
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.remove = dln2_gpio_remove, |
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}; |
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module_platform_driver(dln2_gpio_driver); |
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MODULE_AUTHOR("Daniel Baluta <[email protected]"); |
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MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface"); |
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MODULE_LICENSE("GPL v2"); |
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MODULE_ALIAS("platform:dln2-gpio");
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