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394 lines
9.5 KiB
394 lines
9.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Intel Crystal Cove GPIO Driver |
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* |
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* Copyright (C) 2012, 2014 Intel Corporation. All rights reserved. |
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* |
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* Author: Yang, Bin <[email protected]> |
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*/ |
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#include <linux/bitops.h> |
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#include <linux/gpio/driver.h> |
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#include <linux/interrupt.h> |
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#include <linux/mfd/intel_soc_pmic.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <linux/seq_file.h> |
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#define CRYSTALCOVE_GPIO_NUM 16 |
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#define CRYSTALCOVE_VGPIO_NUM 95 |
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#define UPDATE_IRQ_TYPE BIT(0) |
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#define UPDATE_IRQ_MASK BIT(1) |
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#define GPIO0IRQ 0x0b |
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#define GPIO1IRQ 0x0c |
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#define MGPIO0IRQS0 0x19 |
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#define MGPIO1IRQS0 0x1a |
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#define MGPIO0IRQSX 0x1b |
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#define MGPIO1IRQSX 0x1c |
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#define GPIO0P0CTLO 0x2b |
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#define GPIO0P0CTLI 0x33 |
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#define GPIO1P0CTLO 0x3b |
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#define GPIO1P0CTLI 0x43 |
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#define GPIOPANELCTL 0x52 |
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#define CTLI_INTCNT_DIS (0) |
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#define CTLI_INTCNT_NE (1 << 1) |
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#define CTLI_INTCNT_PE (2 << 1) |
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#define CTLI_INTCNT_BE (3 << 1) |
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#define CTLO_DIR_IN (0) |
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#define CTLO_DIR_OUT (1 << 5) |
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#define CTLO_DRV_CMOS (0) |
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#define CTLO_DRV_OD (1 << 4) |
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#define CTLO_DRV_REN (1 << 3) |
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#define CTLO_RVAL_2KDW (0) |
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#define CTLO_RVAL_2KUP (1 << 1) |
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#define CTLO_RVAL_50KDW (2 << 1) |
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#define CTLO_RVAL_50KUP (3 << 1) |
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#define CTLO_INPUT_SET (CTLO_DRV_CMOS | CTLO_DRV_REN | CTLO_RVAL_2KUP) |
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#define CTLO_OUTPUT_SET (CTLO_DIR_OUT | CTLO_INPUT_SET) |
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enum ctrl_register { |
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CTRL_IN, |
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CTRL_OUT, |
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}; |
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/** |
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* struct crystalcove_gpio - Crystal Cove GPIO controller |
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* @buslock: for bus lock/sync and unlock. |
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* @chip: the abstract gpio_chip structure. |
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* @regmap: the regmap from the parent device. |
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* @update: pending IRQ setting update, to be written to the chip upon unlock. |
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* @intcnt_value: the Interrupt Detect value to be written. |
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* @set_irq_mask: true if the IRQ mask needs to be set, false to clear. |
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*/ |
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struct crystalcove_gpio { |
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struct mutex buslock; /* irq_bus_lock */ |
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struct gpio_chip chip; |
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struct regmap *regmap; |
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int update; |
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int intcnt_value; |
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bool set_irq_mask; |
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}; |
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static inline int to_reg(int gpio, enum ctrl_register reg_type) |
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{ |
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int reg; |
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if (gpio >= CRYSTALCOVE_GPIO_NUM) { |
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/* |
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* Virtual GPIO called from ACPI, for now we only support |
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* the panel ctl. |
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*/ |
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switch (gpio) { |
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case 0x5e: |
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return GPIOPANELCTL; |
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default: |
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return -EOPNOTSUPP; |
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} |
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} |
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if (reg_type == CTRL_IN) { |
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if (gpio < 8) |
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reg = GPIO0P0CTLI; |
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else |
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reg = GPIO1P0CTLI; |
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} else { |
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if (gpio < 8) |
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reg = GPIO0P0CTLO; |
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else |
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reg = GPIO1P0CTLO; |
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} |
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return reg + gpio % 8; |
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} |
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static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, |
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int gpio) |
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{ |
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u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0; |
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int mask = BIT(gpio % 8); |
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if (cg->set_irq_mask) |
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regmap_update_bits(cg->regmap, mirqs0, mask, mask); |
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else |
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regmap_update_bits(cg->regmap, mirqs0, mask, 0); |
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} |
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static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio) |
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{ |
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int reg = to_reg(gpio, CTRL_IN); |
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regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value); |
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} |
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static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio) |
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{ |
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struct crystalcove_gpio *cg = gpiochip_get_data(chip); |
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int reg = to_reg(gpio, CTRL_OUT); |
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if (reg < 0) |
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return 0; |
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return regmap_write(cg->regmap, reg, CTLO_INPUT_SET); |
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} |
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static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, |
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int value) |
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{ |
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struct crystalcove_gpio *cg = gpiochip_get_data(chip); |
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int reg = to_reg(gpio, CTRL_OUT); |
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if (reg < 0) |
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return 0; |
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return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value); |
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} |
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static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio) |
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{ |
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struct crystalcove_gpio *cg = gpiochip_get_data(chip); |
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unsigned int val; |
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int ret, reg = to_reg(gpio, CTRL_IN); |
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if (reg < 0) |
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return 0; |
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ret = regmap_read(cg->regmap, reg, &val); |
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if (ret) |
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return ret; |
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return val & 0x1; |
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} |
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static void crystalcove_gpio_set(struct gpio_chip *chip, |
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unsigned int gpio, int value) |
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{ |
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struct crystalcove_gpio *cg = gpiochip_get_data(chip); |
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int reg = to_reg(gpio, CTRL_OUT); |
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if (reg < 0) |
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return; |
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if (value) |
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regmap_update_bits(cg->regmap, reg, 1, 1); |
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else |
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regmap_update_bits(cg->regmap, reg, 1, 0); |
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} |
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static int crystalcove_irq_type(struct irq_data *data, unsigned int type) |
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{ |
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struct crystalcove_gpio *cg = |
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gpiochip_get_data(irq_data_get_irq_chip_data(data)); |
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if (data->hwirq >= CRYSTALCOVE_GPIO_NUM) |
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return 0; |
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switch (type) { |
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case IRQ_TYPE_NONE: |
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cg->intcnt_value = CTLI_INTCNT_DIS; |
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break; |
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case IRQ_TYPE_EDGE_BOTH: |
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cg->intcnt_value = CTLI_INTCNT_BE; |
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break; |
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case IRQ_TYPE_EDGE_RISING: |
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cg->intcnt_value = CTLI_INTCNT_PE; |
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break; |
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case IRQ_TYPE_EDGE_FALLING: |
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cg->intcnt_value = CTLI_INTCNT_NE; |
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break; |
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default: |
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return -EINVAL; |
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} |
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cg->update |= UPDATE_IRQ_TYPE; |
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return 0; |
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} |
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static void crystalcove_bus_lock(struct irq_data *data) |
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{ |
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struct crystalcove_gpio *cg = |
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gpiochip_get_data(irq_data_get_irq_chip_data(data)); |
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mutex_lock(&cg->buslock); |
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} |
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static void crystalcove_bus_sync_unlock(struct irq_data *data) |
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{ |
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struct crystalcove_gpio *cg = |
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gpiochip_get_data(irq_data_get_irq_chip_data(data)); |
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int gpio = data->hwirq; |
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if (cg->update & UPDATE_IRQ_TYPE) |
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crystalcove_update_irq_ctrl(cg, gpio); |
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if (cg->update & UPDATE_IRQ_MASK) |
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crystalcove_update_irq_mask(cg, gpio); |
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cg->update = 0; |
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mutex_unlock(&cg->buslock); |
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} |
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static void crystalcove_irq_unmask(struct irq_data *data) |
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{ |
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struct crystalcove_gpio *cg = |
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gpiochip_get_data(irq_data_get_irq_chip_data(data)); |
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if (data->hwirq < CRYSTALCOVE_GPIO_NUM) { |
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cg->set_irq_mask = false; |
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cg->update |= UPDATE_IRQ_MASK; |
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} |
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} |
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static void crystalcove_irq_mask(struct irq_data *data) |
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{ |
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struct crystalcove_gpio *cg = |
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gpiochip_get_data(irq_data_get_irq_chip_data(data)); |
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if (data->hwirq < CRYSTALCOVE_GPIO_NUM) { |
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cg->set_irq_mask = true; |
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cg->update |= UPDATE_IRQ_MASK; |
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} |
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} |
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static struct irq_chip crystalcove_irqchip = { |
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.name = "Crystal Cove", |
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.irq_mask = crystalcove_irq_mask, |
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.irq_unmask = crystalcove_irq_unmask, |
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.irq_set_type = crystalcove_irq_type, |
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.irq_bus_lock = crystalcove_bus_lock, |
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.irq_bus_sync_unlock = crystalcove_bus_sync_unlock, |
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.flags = IRQCHIP_SKIP_SET_WAKE, |
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}; |
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static irqreturn_t crystalcove_gpio_irq_handler(int irq, void *data) |
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{ |
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struct crystalcove_gpio *cg = data; |
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unsigned long pending; |
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unsigned int p0, p1; |
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int gpio; |
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unsigned int virq; |
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if (regmap_read(cg->regmap, GPIO0IRQ, &p0) || |
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regmap_read(cg->regmap, GPIO1IRQ, &p1)) |
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return IRQ_NONE; |
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regmap_write(cg->regmap, GPIO0IRQ, p0); |
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regmap_write(cg->regmap, GPIO1IRQ, p1); |
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pending = p0 | p1 << 8; |
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for_each_set_bit(gpio, &pending, CRYSTALCOVE_GPIO_NUM) { |
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virq = irq_find_mapping(cg->chip.irq.domain, gpio); |
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handle_nested_irq(virq); |
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} |
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return IRQ_HANDLED; |
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} |
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static void crystalcove_gpio_dbg_show(struct seq_file *s, |
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struct gpio_chip *chip) |
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{ |
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struct crystalcove_gpio *cg = gpiochip_get_data(chip); |
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int gpio, offset; |
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unsigned int ctlo, ctli, mirqs0, mirqsx, irq; |
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for (gpio = 0; gpio < CRYSTALCOVE_GPIO_NUM; gpio++) { |
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regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); |
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regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli); |
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regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0, |
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&mirqs0); |
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regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX, |
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&mirqsx); |
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regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ, |
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&irq); |
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offset = gpio % 8; |
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seq_printf(s, " gpio-%-2d %s %s %s %s ctlo=%2x,%s %s %s\n", |
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gpio, ctlo & CTLO_DIR_OUT ? "out" : "in ", |
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ctli & 0x1 ? "hi" : "lo", |
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ctli & CTLI_INTCNT_NE ? "fall" : " ", |
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ctli & CTLI_INTCNT_PE ? "rise" : " ", |
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ctlo, |
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mirqs0 & BIT(offset) ? "s0 mask " : "s0 unmask", |
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mirqsx & BIT(offset) ? "sx mask " : "sx unmask", |
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irq & BIT(offset) ? "pending" : " "); |
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} |
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} |
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static int crystalcove_gpio_probe(struct platform_device *pdev) |
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{ |
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int irq = platform_get_irq(pdev, 0); |
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struct crystalcove_gpio *cg; |
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int retval; |
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struct device *dev = pdev->dev.parent; |
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struct intel_soc_pmic *pmic = dev_get_drvdata(dev); |
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struct gpio_irq_chip *girq; |
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if (irq < 0) |
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return irq; |
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cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL); |
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if (!cg) |
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return -ENOMEM; |
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platform_set_drvdata(pdev, cg); |
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mutex_init(&cg->buslock); |
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cg->chip.label = KBUILD_MODNAME; |
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cg->chip.direction_input = crystalcove_gpio_dir_in; |
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cg->chip.direction_output = crystalcove_gpio_dir_out; |
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cg->chip.get = crystalcove_gpio_get; |
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cg->chip.set = crystalcove_gpio_set; |
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cg->chip.base = -1; |
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cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM; |
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cg->chip.can_sleep = true; |
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cg->chip.parent = dev; |
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cg->chip.dbg_show = crystalcove_gpio_dbg_show; |
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cg->regmap = pmic->regmap; |
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girq = &cg->chip.irq; |
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girq->chip = &crystalcove_irqchip; |
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/* This will let us handle the parent IRQ in the driver */ |
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girq->parent_handler = NULL; |
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girq->num_parents = 0; |
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girq->parents = NULL; |
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girq->default_type = IRQ_TYPE_NONE; |
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girq->handler = handle_simple_irq; |
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girq->threaded = true; |
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retval = devm_request_threaded_irq(&pdev->dev, irq, NULL, |
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crystalcove_gpio_irq_handler, |
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IRQF_ONESHOT, KBUILD_MODNAME, cg); |
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if (retval) { |
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dev_warn(&pdev->dev, "request irq failed: %d\n", retval); |
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return retval; |
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} |
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retval = devm_gpiochip_add_data(&pdev->dev, &cg->chip, cg); |
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if (retval) { |
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dev_warn(&pdev->dev, "add gpio chip error: %d\n", retval); |
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return retval; |
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} |
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return 0; |
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} |
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static struct platform_driver crystalcove_gpio_driver = { |
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.probe = crystalcove_gpio_probe, |
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.driver = { |
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.name = "crystal_cove_gpio", |
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}, |
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}; |
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module_platform_driver(crystalcove_gpio_driver); |
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MODULE_AUTHOR("Yang, Bin <[email protected]>"); |
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MODULE_DESCRIPTION("Intel Crystal Cove GPIO Driver"); |
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MODULE_LICENSE("GPL v2");
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