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157 lines
4.7 KiB
157 lines
4.7 KiB
/* SPDX-License-Identifier: GPL-2.0+ */ |
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#ifndef __CF_FSI_FW_H |
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#define __CF_FSI_FW_H |
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/* |
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* uCode file layout |
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* |
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* 0000...03ff : m68k exception vectors |
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* 0400...04ff : Header info & boot config block |
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* 0500....... : Code & stack |
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*/ |
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/* |
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* Header info & boot config area |
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* |
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* The Header info is built into the ucode and provide version and |
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* platform information. |
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* |
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* the Boot config needs to be adjusted by the ARM prior to starting |
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* the ucode if the Command/Status area isn't at 0x320000 in CF space |
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* (ie. beginning of SRAM). |
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*/ |
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#define HDR_OFFSET 0x400 |
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/* Info: Signature & version */ |
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#define HDR_SYS_SIG 0x00 /* 2 bytes system signature */ |
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#define SYS_SIG_SHARED 0x5348 |
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#define SYS_SIG_SPLIT 0x5350 |
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#define HDR_FW_VERS 0x02 /* 2 bytes Major.Minor */ |
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#define HDR_API_VERS 0x04 /* 2 bytes Major.Minor */ |
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#define API_VERSION_MAJ 2 /* Current version */ |
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#define API_VERSION_MIN 1 |
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#define HDR_FW_OPTIONS 0x08 /* 4 bytes option flags */ |
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#define FW_OPTION_TRACE_EN 0x00000001 /* FW tracing enabled */ |
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#define FW_OPTION_CONT_CLOCK 0x00000002 /* Continuous clocking supported */ |
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#define HDR_FW_SIZE 0x10 /* 4 bytes size for combo image */ |
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/* Boot Config: Address of Command/Status area */ |
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#define HDR_CMD_STAT_AREA 0x80 /* 4 bytes CF address */ |
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#define HDR_FW_CONTROL 0x84 /* 4 bytes control flags */ |
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#define FW_CONTROL_CONT_CLOCK 0x00000002 /* Continuous clocking enabled */ |
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#define FW_CONTROL_DUMMY_RD 0x00000004 /* Extra dummy read (AST2400) */ |
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#define FW_CONTROL_USE_STOP 0x00000008 /* Use STOP instructions */ |
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#define HDR_CLOCK_GPIO_VADDR 0x90 /* 2 bytes offset from GPIO base */ |
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#define HDR_CLOCK_GPIO_DADDR 0x92 /* 2 bytes offset from GPIO base */ |
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#define HDR_DATA_GPIO_VADDR 0x94 /* 2 bytes offset from GPIO base */ |
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#define HDR_DATA_GPIO_DADDR 0x96 /* 2 bytes offset from GPIO base */ |
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#define HDR_TRANS_GPIO_VADDR 0x98 /* 2 bytes offset from GPIO base */ |
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#define HDR_TRANS_GPIO_DADDR 0x9a /* 2 bytes offset from GPIO base */ |
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#define HDR_CLOCK_GPIO_BIT 0x9c /* 1 byte bit number */ |
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#define HDR_DATA_GPIO_BIT 0x9d /* 1 byte bit number */ |
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#define HDR_TRANS_GPIO_BIT 0x9e /* 1 byte bit number */ |
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/* |
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* Command/Status area layout: Main part |
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*/ |
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/* Command/Status register: |
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* |
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* +---------------------------+ |
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* | STAT | RLEN | CLEN | CMD | |
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* | 8 | 8 | 8 | 8 | |
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* +---------------------------+ |
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* | | | | |
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* status | | | |
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* Response len | | |
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* (in bits) | | |
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* | | |
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* Command len | |
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* (in bits) | |
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* | |
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* Command code |
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* |
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* Due to the big endian layout, that means that a byte read will |
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* return the status byte |
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*/ |
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#define CMD_STAT_REG 0x00 |
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#define CMD_REG_CMD_MASK 0x000000ff |
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#define CMD_REG_CMD_SHIFT 0 |
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#define CMD_NONE 0x00 |
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#define CMD_COMMAND 0x01 |
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#define CMD_BREAK 0x02 |
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#define CMD_IDLE_CLOCKS 0x03 /* clen = #clocks */ |
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#define CMD_INVALID 0xff |
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#define CMD_REG_CLEN_MASK 0x0000ff00 |
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#define CMD_REG_CLEN_SHIFT 8 |
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#define CMD_REG_RLEN_MASK 0x00ff0000 |
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#define CMD_REG_RLEN_SHIFT 16 |
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#define CMD_REG_STAT_MASK 0xff000000 |
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#define CMD_REG_STAT_SHIFT 24 |
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#define STAT_WORKING 0x00 |
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#define STAT_COMPLETE 0x01 |
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#define STAT_ERR_INVAL_CMD 0x80 |
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#define STAT_ERR_INVAL_IRQ 0x81 |
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#define STAT_ERR_MTOE 0x82 |
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/* Response tag & CRC */ |
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#define STAT_RTAG 0x04 |
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/* Response CRC */ |
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#define STAT_RCRC 0x05 |
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/* Echo and Send delay */ |
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#define ECHO_DLY_REG 0x08 |
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#define SEND_DLY_REG 0x09 |
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/* Command data area |
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* |
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* Last byte of message must be left aligned |
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*/ |
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#define CMD_DATA 0x10 /* 64 bit of data */ |
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/* Response data area, right aligned, unused top bits are 1 */ |
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#define RSP_DATA 0x20 /* 32 bit of data */ |
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/* Misc */ |
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#define INT_CNT 0x30 /* 32-bit interrupt count */ |
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#define BAD_INT_VEC 0x34 /* 32-bit bad interrupt vector # */ |
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#define CF_STARTED 0x38 /* byte, set to -1 when copro started */ |
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#define CLK_CNT 0x3c /* 32-bit, clock count (debug only) */ |
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/* |
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* SRAM layout: GPIO arbitration part |
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*/ |
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#define ARB_REG 0x40 |
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#define ARB_ARM_REQ 0x01 |
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#define ARB_ARM_ACK 0x02 |
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/* Misc2 */ |
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#define CF_RESET_D0 0x50 |
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#define CF_RESET_D1 0x54 |
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#define BAD_INT_S0 0x58 |
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#define BAD_INT_S1 0x5c |
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#define STOP_CNT 0x60 |
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/* Internal */ |
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/* |
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* SRAM layout: Trace buffer (debug builds only) |
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*/ |
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#define TRACEBUF 0x100 |
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#define TR_CLKOBIT0 0xc0 |
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#define TR_CLKOBIT1 0xc1 |
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#define TR_CLKOSTART 0x82 |
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#define TR_OLEN 0x83 /* + len */ |
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#define TR_CLKZ 0x84 /* + count */ |
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#define TR_CLKWSTART 0x85 |
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#define TR_CLKTAG 0x86 /* + tag */ |
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#define TR_CLKDATA 0x87 /* + len */ |
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#define TR_CLKCRC 0x88 /* + raw crc */ |
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#define TR_CLKIBIT0 0x90 |
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#define TR_CLKIBIT1 0x91 |
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#define TR_END 0xff |
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#endif /* __CF_FSI_FW_H */ |
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