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520 lines
16 KiB
520 lines
16 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* |
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* Driver Header File for FPGA Device Feature List (DFL) Support |
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* |
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* Copyright (C) 2017-2018 Intel Corporation, Inc. |
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* |
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* Authors: |
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* Kang Luwei <[email protected]> |
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* Zhang Yi <[email protected]> |
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* Wu Hao <[email protected]> |
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* Xiao Guangrong <[email protected]> |
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*/ |
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#ifndef __FPGA_DFL_H |
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#define __FPGA_DFL_H |
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#include <linux/bitfield.h> |
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#include <linux/cdev.h> |
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#include <linux/delay.h> |
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#include <linux/eventfd.h> |
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#include <linux/fs.h> |
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#include <linux/interrupt.h> |
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#include <linux/iopoll.h> |
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#include <linux/io-64-nonatomic-lo-hi.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/uuid.h> |
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#include <linux/fpga/fpga-region.h> |
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/* maximum supported number of ports */ |
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#define MAX_DFL_FPGA_PORT_NUM 4 |
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/* plus one for fme device */ |
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#define MAX_DFL_FEATURE_DEV_NUM (MAX_DFL_FPGA_PORT_NUM + 1) |
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/* Reserved 0xfe for Header Group Register and 0xff for AFU */ |
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#define FEATURE_ID_FIU_HEADER 0xfe |
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#define FEATURE_ID_AFU 0xff |
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#define FME_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER |
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#define FME_FEATURE_ID_THERMAL_MGMT 0x1 |
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#define FME_FEATURE_ID_POWER_MGMT 0x2 |
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#define FME_FEATURE_ID_GLOBAL_IPERF 0x3 |
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#define FME_FEATURE_ID_GLOBAL_ERR 0x4 |
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#define FME_FEATURE_ID_PR_MGMT 0x5 |
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#define FME_FEATURE_ID_HSSI 0x6 |
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#define FME_FEATURE_ID_GLOBAL_DPERF 0x7 |
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#define PORT_FEATURE_ID_HEADER FEATURE_ID_FIU_HEADER |
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#define PORT_FEATURE_ID_AFU FEATURE_ID_AFU |
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#define PORT_FEATURE_ID_ERROR 0x10 |
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#define PORT_FEATURE_ID_UMSG 0x11 |
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#define PORT_FEATURE_ID_UINT 0x12 |
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#define PORT_FEATURE_ID_STP 0x13 |
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/* |
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* Device Feature Header Register Set |
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* |
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* For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. |
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* For AFUs, they have DFH + GUID as common header registers. |
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* For private features, they only have DFH register as common header. |
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*/ |
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#define DFH 0x0 |
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#define GUID_L 0x8 |
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#define GUID_H 0x10 |
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#define NEXT_AFU 0x18 |
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#define DFH_SIZE 0x8 |
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/* Device Feature Header Register Bitfield */ |
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#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ |
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#define DFH_ID_FIU_FME 0 |
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#define DFH_ID_FIU_PORT 1 |
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#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ |
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#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ |
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#define DFH_EOL BIT_ULL(40) /* End of list */ |
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#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ |
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#define DFH_TYPE_AFU 1 |
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#define DFH_TYPE_PRIVATE 3 |
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#define DFH_TYPE_FIU 4 |
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/* Next AFU Register Bitfield */ |
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#define NEXT_AFU_NEXT_DFH_OFST GENMASK_ULL(23, 0) /* Offset to next AFU */ |
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/* FME Header Register Set */ |
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#define FME_HDR_DFH DFH |
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#define FME_HDR_GUID_L GUID_L |
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#define FME_HDR_GUID_H GUID_H |
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#define FME_HDR_NEXT_AFU NEXT_AFU |
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#define FME_HDR_CAP 0x30 |
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#define FME_HDR_PORT_OFST(n) (0x38 + ((n) * 0x8)) |
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#define FME_HDR_BITSTREAM_ID 0x60 |
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#define FME_HDR_BITSTREAM_MD 0x68 |
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/* FME Fab Capability Register Bitfield */ |
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#define FME_CAP_FABRIC_VERID GENMASK_ULL(7, 0) /* Fabric version ID */ |
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#define FME_CAP_SOCKET_ID BIT_ULL(8) /* Socket ID */ |
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#define FME_CAP_PCIE0_LINK_AVL BIT_ULL(12) /* PCIE0 Link */ |
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#define FME_CAP_PCIE1_LINK_AVL BIT_ULL(13) /* PCIE1 Link */ |
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#define FME_CAP_COHR_LINK_AVL BIT_ULL(14) /* Coherent Link */ |
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#define FME_CAP_IOMMU_AVL BIT_ULL(16) /* IOMMU available */ |
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#define FME_CAP_NUM_PORTS GENMASK_ULL(19, 17) /* Number of ports */ |
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#define FME_CAP_ADDR_WIDTH GENMASK_ULL(29, 24) /* Address bus width */ |
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#define FME_CAP_CACHE_SIZE GENMASK_ULL(43, 32) /* cache size in KB */ |
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#define FME_CAP_CACHE_ASSOC GENMASK_ULL(47, 44) /* Associativity */ |
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/* FME Port Offset Register Bitfield */ |
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/* Offset to port device feature header */ |
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#define FME_PORT_OFST_DFH_OFST GENMASK_ULL(23, 0) |
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/* PCI Bar ID for this port */ |
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#define FME_PORT_OFST_BAR_ID GENMASK_ULL(34, 32) |
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/* AFU MMIO access permission. 1 - VF, 0 - PF. */ |
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#define FME_PORT_OFST_ACC_CTRL BIT_ULL(55) |
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#define FME_PORT_OFST_ACC_PF 0 |
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#define FME_PORT_OFST_ACC_VF 1 |
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#define FME_PORT_OFST_IMP BIT_ULL(60) |
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/* FME Error Capability Register */ |
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#define FME_ERROR_CAP 0x70 |
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/* FME Error Capability Register Bitfield */ |
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#define FME_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */ |
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#define FME_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */ |
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/* PORT Header Register Set */ |
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#define PORT_HDR_DFH DFH |
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#define PORT_HDR_GUID_L GUID_L |
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#define PORT_HDR_GUID_H GUID_H |
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#define PORT_HDR_NEXT_AFU NEXT_AFU |
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#define PORT_HDR_CAP 0x30 |
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#define PORT_HDR_CTRL 0x38 |
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#define PORT_HDR_STS 0x40 |
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#define PORT_HDR_USRCLK_CMD0 0x50 |
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#define PORT_HDR_USRCLK_CMD1 0x58 |
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#define PORT_HDR_USRCLK_STS0 0x60 |
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#define PORT_HDR_USRCLK_STS1 0x68 |
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/* Port Capability Register Bitfield */ |
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#define PORT_CAP_PORT_NUM GENMASK_ULL(1, 0) /* ID of this port */ |
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#define PORT_CAP_MMIO_SIZE GENMASK_ULL(23, 8) /* MMIO size in KB */ |
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#define PORT_CAP_SUPP_INT_NUM GENMASK_ULL(35, 32) /* Interrupts num */ |
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/* Port Control Register Bitfield */ |
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#define PORT_CTRL_SFTRST BIT_ULL(0) /* Port soft reset */ |
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/* Latency tolerance reporting. '1' >= 40us, '0' < 40us.*/ |
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#define PORT_CTRL_LATENCY BIT_ULL(2) |
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#define PORT_CTRL_SFTRST_ACK BIT_ULL(4) /* HW ack for reset */ |
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/* Port Status Register Bitfield */ |
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#define PORT_STS_AP2_EVT BIT_ULL(13) /* AP2 event detected */ |
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#define PORT_STS_AP1_EVT BIT_ULL(12) /* AP1 event detected */ |
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#define PORT_STS_PWR_STATE GENMASK_ULL(11, 8) /* AFU power states */ |
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#define PORT_STS_PWR_STATE_NORM 0 |
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#define PORT_STS_PWR_STATE_AP1 1 /* 50% throttling */ |
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#define PORT_STS_PWR_STATE_AP2 2 /* 90% throttling */ |
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#define PORT_STS_PWR_STATE_AP6 6 /* 100% throttling */ |
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/* Port Error Capability Register */ |
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#define PORT_ERROR_CAP 0x38 |
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/* Port Error Capability Register Bitfield */ |
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#define PORT_ERROR_CAP_SUPP_INT BIT_ULL(0) /* Interrupt Support */ |
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#define PORT_ERROR_CAP_INT_VECT GENMASK_ULL(12, 1) /* Interrupt vector */ |
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/* Port Uint Capability Register */ |
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#define PORT_UINT_CAP 0x8 |
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/* Port Uint Capability Register Bitfield */ |
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#define PORT_UINT_CAP_INT_NUM GENMASK_ULL(11, 0) /* Interrupts num */ |
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#define PORT_UINT_CAP_FST_VECT GENMASK_ULL(23, 12) /* First Vector */ |
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/** |
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* struct dfl_fpga_port_ops - port ops |
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* |
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* @name: name of this port ops, to match with port platform device. |
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* @owner: pointer to the module which owns this port ops. |
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* @node: node to link port ops to global list. |
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* @get_id: get port id from hardware. |
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* @enable_set: enable/disable the port. |
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*/ |
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struct dfl_fpga_port_ops { |
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const char *name; |
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struct module *owner; |
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struct list_head node; |
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int (*get_id)(struct platform_device *pdev); |
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int (*enable_set)(struct platform_device *pdev, bool enable); |
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}; |
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void dfl_fpga_port_ops_add(struct dfl_fpga_port_ops *ops); |
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void dfl_fpga_port_ops_del(struct dfl_fpga_port_ops *ops); |
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struct dfl_fpga_port_ops *dfl_fpga_port_ops_get(struct platform_device *pdev); |
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void dfl_fpga_port_ops_put(struct dfl_fpga_port_ops *ops); |
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int dfl_fpga_check_port_id(struct platform_device *pdev, void *pport_id); |
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/** |
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* struct dfl_feature_id - dfl private feature id |
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* |
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* @id: unique dfl private feature id. |
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*/ |
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struct dfl_feature_id { |
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u16 id; |
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}; |
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/** |
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* struct dfl_feature_driver - dfl private feature driver |
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* |
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* @id_table: id_table for dfl private features supported by this driver. |
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* @ops: ops of this dfl private feature driver. |
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*/ |
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struct dfl_feature_driver { |
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const struct dfl_feature_id *id_table; |
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const struct dfl_feature_ops *ops; |
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}; |
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/** |
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* struct dfl_feature_irq_ctx - dfl private feature interrupt context |
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* |
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* @irq: Linux IRQ number of this interrupt. |
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* @trigger: eventfd context to signal when interrupt happens. |
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* @name: irq name needed when requesting irq. |
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*/ |
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struct dfl_feature_irq_ctx { |
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int irq; |
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struct eventfd_ctx *trigger; |
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char *name; |
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}; |
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/** |
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* struct dfl_feature - sub feature of the feature devices |
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* |
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* @dev: ptr to pdev of the feature device which has the sub feature. |
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* @id: sub feature id. |
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* @resource_index: each sub feature has one mmio resource for its registers. |
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* this index is used to find its mmio resource from the |
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* feature dev (platform device)'s reources. |
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* @ioaddr: mapped mmio resource address. |
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* @irq_ctx: interrupt context list. |
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* @nr_irqs: number of interrupt contexts. |
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* @ops: ops of this sub feature. |
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* @ddev: ptr to the dfl device of this sub feature. |
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* @priv: priv data of this feature. |
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*/ |
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struct dfl_feature { |
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struct platform_device *dev; |
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u16 id; |
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int resource_index; |
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void __iomem *ioaddr; |
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struct dfl_feature_irq_ctx *irq_ctx; |
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unsigned int nr_irqs; |
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const struct dfl_feature_ops *ops; |
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struct dfl_device *ddev; |
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void *priv; |
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}; |
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#define FEATURE_DEV_ID_UNUSED (-1) |
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/** |
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* struct dfl_feature_platform_data - platform data for feature devices |
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* |
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* @node: node to link feature devs to container device's port_dev_list. |
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* @lock: mutex to protect platform data. |
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* @cdev: cdev of feature dev. |
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* @dev: ptr to platform device linked with this platform data. |
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* @dfl_cdev: ptr to container device. |
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* @id: id used for this feature device. |
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* @disable_count: count for port disable. |
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* @excl_open: set on feature device exclusive open. |
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* @open_count: count for feature device open. |
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* @num: number for sub features. |
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* @private: ptr to feature dev private data. |
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* @features: sub features of this feature dev. |
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*/ |
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struct dfl_feature_platform_data { |
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struct list_head node; |
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struct mutex lock; |
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struct cdev cdev; |
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struct platform_device *dev; |
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struct dfl_fpga_cdev *dfl_cdev; |
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int id; |
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unsigned int disable_count; |
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bool excl_open; |
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int open_count; |
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void *private; |
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int num; |
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struct dfl_feature features[]; |
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}; |
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static inline |
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int dfl_feature_dev_use_begin(struct dfl_feature_platform_data *pdata, |
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bool excl) |
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{ |
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if (pdata->excl_open) |
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return -EBUSY; |
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if (excl) { |
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if (pdata->open_count) |
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return -EBUSY; |
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pdata->excl_open = true; |
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} |
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pdata->open_count++; |
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return 0; |
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} |
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static inline |
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void dfl_feature_dev_use_end(struct dfl_feature_platform_data *pdata) |
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{ |
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pdata->excl_open = false; |
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if (WARN_ON(pdata->open_count <= 0)) |
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return; |
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pdata->open_count--; |
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} |
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static inline |
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int dfl_feature_dev_use_count(struct dfl_feature_platform_data *pdata) |
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{ |
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return pdata->open_count; |
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} |
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static inline |
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void dfl_fpga_pdata_set_private(struct dfl_feature_platform_data *pdata, |
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void *private) |
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{ |
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pdata->private = private; |
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} |
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static inline |
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void *dfl_fpga_pdata_get_private(struct dfl_feature_platform_data *pdata) |
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{ |
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return pdata->private; |
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} |
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struct dfl_feature_ops { |
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int (*init)(struct platform_device *pdev, struct dfl_feature *feature); |
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void (*uinit)(struct platform_device *pdev, |
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struct dfl_feature *feature); |
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long (*ioctl)(struct platform_device *pdev, struct dfl_feature *feature, |
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unsigned int cmd, unsigned long arg); |
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}; |
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#define DFL_FPGA_FEATURE_DEV_FME "dfl-fme" |
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#define DFL_FPGA_FEATURE_DEV_PORT "dfl-port" |
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void dfl_fpga_dev_feature_uinit(struct platform_device *pdev); |
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int dfl_fpga_dev_feature_init(struct platform_device *pdev, |
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struct dfl_feature_driver *feature_drvs); |
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int dfl_fpga_dev_ops_register(struct platform_device *pdev, |
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const struct file_operations *fops, |
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struct module *owner); |
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void dfl_fpga_dev_ops_unregister(struct platform_device *pdev); |
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static inline |
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struct platform_device *dfl_fpga_inode_to_feature_dev(struct inode *inode) |
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{ |
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struct dfl_feature_platform_data *pdata; |
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pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data, |
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cdev); |
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return pdata->dev; |
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} |
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#define dfl_fpga_dev_for_each_feature(pdata, feature) \ |
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for ((feature) = (pdata)->features; \ |
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(feature) < (pdata)->features + (pdata)->num; (feature)++) |
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static inline |
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struct dfl_feature *dfl_get_feature_by_id(struct device *dev, u16 id) |
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{ |
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev); |
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struct dfl_feature *feature; |
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dfl_fpga_dev_for_each_feature(pdata, feature) |
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if (feature->id == id) |
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return feature; |
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return NULL; |
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} |
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static inline |
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void __iomem *dfl_get_feature_ioaddr_by_id(struct device *dev, u16 id) |
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{ |
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struct dfl_feature *feature = dfl_get_feature_by_id(dev, id); |
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if (feature && feature->ioaddr) |
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return feature->ioaddr; |
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WARN_ON(1); |
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return NULL; |
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} |
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static inline bool is_dfl_feature_present(struct device *dev, u16 id) |
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{ |
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return !!dfl_get_feature_ioaddr_by_id(dev, id); |
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} |
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static inline |
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struct device *dfl_fpga_pdata_to_parent(struct dfl_feature_platform_data *pdata) |
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{ |
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return pdata->dev->dev.parent->parent; |
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} |
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static inline bool dfl_feature_is_fme(void __iomem *base) |
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{ |
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u64 v = readq(base + DFH); |
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return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && |
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(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME); |
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} |
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static inline bool dfl_feature_is_port(void __iomem *base) |
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{ |
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u64 v = readq(base + DFH); |
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return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) && |
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(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT); |
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} |
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static inline u8 dfl_feature_revision(void __iomem *base) |
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{ |
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return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH)); |
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} |
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/** |
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* struct dfl_fpga_enum_info - DFL FPGA enumeration information |
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* |
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* @dev: parent device. |
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* @dfls: list of device feature lists. |
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* @nr_irqs: number of irqs for all feature devices. |
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* @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers. |
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*/ |
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struct dfl_fpga_enum_info { |
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struct device *dev; |
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struct list_head dfls; |
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unsigned int nr_irqs; |
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int *irq_table; |
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}; |
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/** |
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* struct dfl_fpga_enum_dfl - DFL FPGA enumeration device feature list info |
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* |
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* @start: base address of this device feature list. |
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* @len: size of this device feature list. |
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* @node: node in list of device feature lists. |
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*/ |
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struct dfl_fpga_enum_dfl { |
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resource_size_t start; |
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resource_size_t len; |
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struct list_head node; |
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}; |
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struct dfl_fpga_enum_info *dfl_fpga_enum_info_alloc(struct device *dev); |
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int dfl_fpga_enum_info_add_dfl(struct dfl_fpga_enum_info *info, |
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resource_size_t start, resource_size_t len); |
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int dfl_fpga_enum_info_add_irq(struct dfl_fpga_enum_info *info, |
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unsigned int nr_irqs, int *irq_table); |
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void dfl_fpga_enum_info_free(struct dfl_fpga_enum_info *info); |
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/** |
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* struct dfl_fpga_cdev - container device of DFL based FPGA |
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* |
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* @parent: parent device of this container device. |
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* @region: base fpga region. |
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* @fme_dev: FME feature device under this container device. |
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* @lock: mutex lock to protect the port device list. |
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* @port_dev_list: list of all port feature devices under this container device. |
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* @released_port_num: released port number under this container device. |
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*/ |
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struct dfl_fpga_cdev { |
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struct device *parent; |
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struct fpga_region *region; |
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struct device *fme_dev; |
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struct mutex lock; |
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struct list_head port_dev_list; |
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int released_port_num; |
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}; |
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struct dfl_fpga_cdev * |
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dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info); |
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void dfl_fpga_feature_devs_remove(struct dfl_fpga_cdev *cdev); |
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/* |
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* need to drop the device reference with put_device() after use port platform |
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* device returned by __dfl_fpga_cdev_find_port and dfl_fpga_cdev_find_port |
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* functions. |
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*/ |
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struct platform_device * |
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__dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, |
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int (*match)(struct platform_device *, void *)); |
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static inline struct platform_device * |
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dfl_fpga_cdev_find_port(struct dfl_fpga_cdev *cdev, void *data, |
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int (*match)(struct platform_device *, void *)) |
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{ |
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struct platform_device *pdev; |
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mutex_lock(&cdev->lock); |
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pdev = __dfl_fpga_cdev_find_port(cdev, data, match); |
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mutex_unlock(&cdev->lock); |
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return pdev; |
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} |
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int dfl_fpga_cdev_release_port(struct dfl_fpga_cdev *cdev, int port_id); |
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int dfl_fpga_cdev_assign_port(struct dfl_fpga_cdev *cdev, int port_id); |
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void dfl_fpga_cdev_config_ports_pf(struct dfl_fpga_cdev *cdev); |
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int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vf); |
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int dfl_fpga_set_irq_triggers(struct dfl_feature *feature, unsigned int start, |
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unsigned int count, int32_t *fds); |
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long dfl_feature_ioctl_get_num_irqs(struct platform_device *pdev, |
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struct dfl_feature *feature, |
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unsigned long arg); |
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long dfl_feature_ioctl_set_irq(struct platform_device *pdev, |
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struct dfl_feature *feature, |
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unsigned long arg); |
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#endif /* __FPGA_DFL_H */
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