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231 lines
5.8 KiB
231 lines
5.8 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* FPGA to/from HPS Bridge Driver for Altera SoCFPGA Devices |
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* |
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* Copyright (C) 2013-2016 Altera Corporation, All Rights Reserved. |
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* |
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* Includes this patch from the mailing list: |
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* fpga: altera-hps2fpga: fix HPS2FPGA bridge visibility to L3 masters |
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* Signed-off-by: Anatolij Gustschin <[email protected]> |
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*/ |
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/* |
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* This driver manages bridges on a Altera SOCFPGA between the ARM host |
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* processor system (HPS) and the embedded FPGA. |
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* |
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* This driver supports enabling and disabling of the configured ports, which |
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* allows for safe reprogramming of the FPGA, assuming that the new FPGA image |
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* uses the same port configuration. Bridges must be disabled before |
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* reprogramming the FPGA and re-enabled after the FPGA has been programmed. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/fpga/fpga-bridge.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/module.h> |
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#include <linux/of_platform.h> |
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#include <linux/regmap.h> |
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#include <linux/reset.h> |
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#include <linux/spinlock.h> |
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#define ALT_L3_REMAP_OFST 0x0 |
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#define ALT_L3_REMAP_MPUZERO_MSK 0x00000001 |
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#define ALT_L3_REMAP_H2F_MSK 0x00000008 |
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#define ALT_L3_REMAP_LWH2F_MSK 0x00000010 |
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#define HPS2FPGA_BRIDGE_NAME "hps2fpga" |
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#define LWHPS2FPGA_BRIDGE_NAME "lwhps2fpga" |
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#define FPGA2HPS_BRIDGE_NAME "fpga2hps" |
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struct altera_hps2fpga_data { |
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const char *name; |
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struct reset_control *bridge_reset; |
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struct regmap *l3reg; |
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unsigned int remap_mask; |
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struct clk *clk; |
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}; |
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static int alt_hps2fpga_enable_show(struct fpga_bridge *bridge) |
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{ |
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struct altera_hps2fpga_data *priv = bridge->priv; |
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return reset_control_status(priv->bridge_reset); |
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} |
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/* The L3 REMAP register is write only, so keep a cached value. */ |
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static unsigned int l3_remap_shadow; |
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static DEFINE_SPINLOCK(l3_remap_lock); |
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static int _alt_hps2fpga_enable_set(struct altera_hps2fpga_data *priv, |
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bool enable) |
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{ |
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unsigned long flags; |
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int ret; |
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/* bring bridge out of reset */ |
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if (enable) |
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ret = reset_control_deassert(priv->bridge_reset); |
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else |
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ret = reset_control_assert(priv->bridge_reset); |
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if (ret) |
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return ret; |
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/* Allow bridge to be visible to L3 masters or not */ |
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if (priv->remap_mask) { |
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spin_lock_irqsave(&l3_remap_lock, flags); |
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l3_remap_shadow |= ALT_L3_REMAP_MPUZERO_MSK; |
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if (enable) |
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l3_remap_shadow |= priv->remap_mask; |
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else |
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l3_remap_shadow &= ~priv->remap_mask; |
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ret = regmap_write(priv->l3reg, ALT_L3_REMAP_OFST, |
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l3_remap_shadow); |
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spin_unlock_irqrestore(&l3_remap_lock, flags); |
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} |
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return ret; |
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} |
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static int alt_hps2fpga_enable_set(struct fpga_bridge *bridge, bool enable) |
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{ |
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return _alt_hps2fpga_enable_set(bridge->priv, enable); |
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} |
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static const struct fpga_bridge_ops altera_hps2fpga_br_ops = { |
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.enable_set = alt_hps2fpga_enable_set, |
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.enable_show = alt_hps2fpga_enable_show, |
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}; |
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static struct altera_hps2fpga_data hps2fpga_data = { |
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.name = HPS2FPGA_BRIDGE_NAME, |
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.remap_mask = ALT_L3_REMAP_H2F_MSK, |
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}; |
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static struct altera_hps2fpga_data lwhps2fpga_data = { |
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.name = LWHPS2FPGA_BRIDGE_NAME, |
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.remap_mask = ALT_L3_REMAP_LWH2F_MSK, |
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}; |
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static struct altera_hps2fpga_data fpga2hps_data = { |
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.name = FPGA2HPS_BRIDGE_NAME, |
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}; |
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static const struct of_device_id altera_fpga_of_match[] = { |
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{ .compatible = "altr,socfpga-hps2fpga-bridge", |
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.data = &hps2fpga_data }, |
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{ .compatible = "altr,socfpga-lwhps2fpga-bridge", |
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.data = &lwhps2fpga_data }, |
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{ .compatible = "altr,socfpga-fpga2hps-bridge", |
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.data = &fpga2hps_data }, |
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{}, |
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}; |
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static int alt_fpga_bridge_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct altera_hps2fpga_data *priv; |
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const struct of_device_id *of_id; |
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struct fpga_bridge *br; |
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u32 enable; |
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int ret; |
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of_id = of_match_device(altera_fpga_of_match, dev); |
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if (!of_id) { |
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dev_err(dev, "failed to match device\n"); |
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return -ENODEV; |
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} |
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priv = (struct altera_hps2fpga_data *)of_id->data; |
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priv->bridge_reset = of_reset_control_get_exclusive_by_index(dev->of_node, |
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0); |
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if (IS_ERR(priv->bridge_reset)) { |
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dev_err(dev, "Could not get %s reset control\n", priv->name); |
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return PTR_ERR(priv->bridge_reset); |
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} |
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if (priv->remap_mask) { |
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priv->l3reg = syscon_regmap_lookup_by_compatible("altr,l3regs"); |
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if (IS_ERR(priv->l3reg)) { |
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dev_err(dev, "regmap for altr,l3regs lookup failed\n"); |
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return PTR_ERR(priv->l3reg); |
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} |
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} |
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priv->clk = devm_clk_get(dev, NULL); |
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if (IS_ERR(priv->clk)) { |
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dev_err(dev, "no clock specified\n"); |
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return PTR_ERR(priv->clk); |
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} |
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ret = clk_prepare_enable(priv->clk); |
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if (ret) { |
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dev_err(dev, "could not enable clock\n"); |
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return -EBUSY; |
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} |
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if (!of_property_read_u32(dev->of_node, "bridge-enable", &enable)) { |
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if (enable > 1) { |
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dev_warn(dev, "invalid bridge-enable %u > 1\n", enable); |
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} else { |
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dev_info(dev, "%s bridge\n", |
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(enable ? "enabling" : "disabling")); |
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ret = _alt_hps2fpga_enable_set(priv, enable); |
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if (ret) |
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goto err; |
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} |
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} |
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br = devm_fpga_bridge_create(dev, priv->name, |
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&altera_hps2fpga_br_ops, priv); |
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if (!br) { |
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ret = -ENOMEM; |
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goto err; |
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} |
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platform_set_drvdata(pdev, br); |
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ret = fpga_bridge_register(br); |
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if (ret) |
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goto err; |
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return 0; |
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err: |
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clk_disable_unprepare(priv->clk); |
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return ret; |
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} |
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static int alt_fpga_bridge_remove(struct platform_device *pdev) |
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{ |
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struct fpga_bridge *bridge = platform_get_drvdata(pdev); |
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struct altera_hps2fpga_data *priv = bridge->priv; |
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fpga_bridge_unregister(bridge); |
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clk_disable_unprepare(priv->clk); |
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return 0; |
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} |
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MODULE_DEVICE_TABLE(of, altera_fpga_of_match); |
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static struct platform_driver alt_fpga_bridge_driver = { |
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.probe = alt_fpga_bridge_probe, |
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.remove = alt_fpga_bridge_remove, |
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.driver = { |
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.name = "altera_hps2fpga_bridge", |
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.of_match_table = of_match_ptr(altera_fpga_of_match), |
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}, |
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}; |
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module_platform_driver(alt_fpga_bridge_driver); |
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MODULE_DESCRIPTION("Altera SoCFPGA HPS to FPGA Bridge"); |
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MODULE_AUTHOR("Alan Tull <[email protected]>"); |
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MODULE_LICENSE("GPL v2");
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