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747 lines
19 KiB
747 lines
19 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* EDAC driver for Intel(R) Xeon(R) Skylake processors |
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* Copyright (c) 2016, Intel Corporation. |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/processor.h> |
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#include <asm/cpu_device_id.h> |
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#include <asm/intel-family.h> |
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#include <asm/mce.h> |
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|
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#include "edac_module.h" |
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#include "skx_common.h" |
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|
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#define EDAC_MOD_STR "skx_edac" |
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|
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/* |
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* Debug macros |
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*/ |
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#define skx_printk(level, fmt, arg...) \ |
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edac_printk(level, "skx", fmt, ##arg) |
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#define skx_mc_printk(mci, level, fmt, arg...) \ |
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edac_mc_chipset_printk(mci, level, "skx", fmt, ##arg) |
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static struct list_head *skx_edac_list; |
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static u64 skx_tolm, skx_tohm; |
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static int skx_num_sockets; |
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static unsigned int nvdimm_count; |
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|
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#define MASK26 0x3FFFFFF /* Mask for 2^26 */ |
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#define MASK29 0x1FFFFFFF /* Mask for 2^29 */ |
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static struct skx_dev *get_skx_dev(struct pci_bus *bus, u8 idx) |
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{ |
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struct skx_dev *d; |
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|
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list_for_each_entry(d, skx_edac_list, list) { |
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if (d->seg == pci_domain_nr(bus) && d->bus[idx] == bus->number) |
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return d; |
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} |
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|
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return NULL; |
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} |
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enum munittype { |
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CHAN0, CHAN1, CHAN2, SAD_ALL, UTIL_ALL, SAD, |
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ERRCHAN0, ERRCHAN1, ERRCHAN2, |
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}; |
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struct munit { |
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u16 did; |
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u16 devfn[SKX_NUM_IMC]; |
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u8 busidx; |
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u8 per_socket; |
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enum munittype mtype; |
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}; |
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|
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/* |
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* List of PCI device ids that we need together with some device |
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* number and function numbers to tell which memory controller the |
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* device belongs to. |
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*/ |
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static const struct munit skx_all_munits[] = { |
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{ 0x2054, { }, 1, 1, SAD_ALL }, |
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{ 0x2055, { }, 1, 1, UTIL_ALL }, |
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{ 0x2040, { PCI_DEVFN(10, 0), PCI_DEVFN(12, 0) }, 2, 2, CHAN0 }, |
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{ 0x2044, { PCI_DEVFN(10, 4), PCI_DEVFN(12, 4) }, 2, 2, CHAN1 }, |
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{ 0x2048, { PCI_DEVFN(11, 0), PCI_DEVFN(13, 0) }, 2, 2, CHAN2 }, |
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{ 0x2043, { PCI_DEVFN(10, 3), PCI_DEVFN(12, 3) }, 2, 2, ERRCHAN0 }, |
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{ 0x2047, { PCI_DEVFN(10, 7), PCI_DEVFN(12, 7) }, 2, 2, ERRCHAN1 }, |
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{ 0x204b, { PCI_DEVFN(11, 3), PCI_DEVFN(13, 3) }, 2, 2, ERRCHAN2 }, |
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{ 0x208e, { }, 1, 0, SAD }, |
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{ } |
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}; |
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|
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static int get_all_munits(const struct munit *m) |
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{ |
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struct pci_dev *pdev, *prev; |
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struct skx_dev *d; |
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u32 reg; |
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int i = 0, ndev = 0; |
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|
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prev = NULL; |
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for (;;) { |
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pdev = pci_get_device(PCI_VENDOR_ID_INTEL, m->did, prev); |
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if (!pdev) |
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break; |
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ndev++; |
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if (m->per_socket == SKX_NUM_IMC) { |
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for (i = 0; i < SKX_NUM_IMC; i++) |
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if (m->devfn[i] == pdev->devfn) |
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break; |
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if (i == SKX_NUM_IMC) |
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goto fail; |
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} |
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d = get_skx_dev(pdev->bus, m->busidx); |
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if (!d) |
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goto fail; |
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|
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/* Be sure that the device is enabled */ |
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if (unlikely(pci_enable_device(pdev) < 0)) { |
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skx_printk(KERN_ERR, "Couldn't enable device %04x:%04x\n", |
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PCI_VENDOR_ID_INTEL, m->did); |
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goto fail; |
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} |
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|
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switch (m->mtype) { |
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case CHAN0: |
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case CHAN1: |
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case CHAN2: |
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pci_dev_get(pdev); |
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d->imc[i].chan[m->mtype].cdev = pdev; |
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break; |
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case ERRCHAN0: |
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case ERRCHAN1: |
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case ERRCHAN2: |
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pci_dev_get(pdev); |
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d->imc[i].chan[m->mtype - ERRCHAN0].edev = pdev; |
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break; |
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case SAD_ALL: |
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pci_dev_get(pdev); |
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d->sad_all = pdev; |
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break; |
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case UTIL_ALL: |
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pci_dev_get(pdev); |
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d->util_all = pdev; |
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break; |
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case SAD: |
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/* |
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* one of these devices per core, including cores |
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* that don't exist on this SKU. Ignore any that |
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* read a route table of zero, make sure all the |
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* non-zero values match. |
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*/ |
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pci_read_config_dword(pdev, 0xB4, ®); |
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if (reg != 0) { |
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if (d->mcroute == 0) { |
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d->mcroute = reg; |
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} else if (d->mcroute != reg) { |
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skx_printk(KERN_ERR, "mcroute mismatch\n"); |
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goto fail; |
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} |
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} |
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ndev--; |
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break; |
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} |
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|
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prev = pdev; |
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} |
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|
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return ndev; |
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fail: |
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pci_dev_put(pdev); |
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return -ENODEV; |
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} |
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|
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static struct res_config skx_cfg = { |
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.type = SKX, |
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.decs_did = 0x2016, |
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.busno_cfg_offset = 0xcc, |
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}; |
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|
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static const struct x86_cpu_id skx_cpuids[] = { |
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X86_MATCH_INTEL_FAM6_MODEL_STEPPINGS(SKYLAKE_X, X86_STEPPINGS(0x0, 0xf), &skx_cfg), |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(x86cpu, skx_cpuids); |
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|
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static bool skx_check_ecc(u32 mcmtr) |
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{ |
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return !!GET_BITFIELD(mcmtr, 2, 2); |
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} |
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static int skx_get_dimm_config(struct mem_ctl_info *mci, struct res_config *cfg) |
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{ |
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struct skx_pvt *pvt = mci->pvt_info; |
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u32 mtr, mcmtr, amap, mcddrtcfg; |
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struct skx_imc *imc = pvt->imc; |
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struct dimm_info *dimm; |
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int i, j; |
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int ndimms; |
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|
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/* Only the mcmtr on the first channel is effective */ |
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pci_read_config_dword(imc->chan[0].cdev, 0x87c, &mcmtr); |
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|
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for (i = 0; i < SKX_NUM_CHANNELS; i++) { |
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ndimms = 0; |
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pci_read_config_dword(imc->chan[i].cdev, 0x8C, &amap); |
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pci_read_config_dword(imc->chan[i].cdev, 0x400, &mcddrtcfg); |
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for (j = 0; j < SKX_NUM_DIMMS; j++) { |
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dimm = edac_get_dimm(mci, i, j, 0); |
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pci_read_config_dword(imc->chan[i].cdev, |
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0x80 + 4 * j, &mtr); |
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if (IS_DIMM_PRESENT(mtr)) { |
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ndimms += skx_get_dimm_info(mtr, mcmtr, amap, dimm, imc, i, j, cfg); |
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} else if (IS_NVDIMM_PRESENT(mcddrtcfg, j)) { |
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ndimms += skx_get_nvdimm_info(dimm, imc, i, j, |
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EDAC_MOD_STR); |
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nvdimm_count++; |
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} |
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} |
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if (ndimms && !skx_check_ecc(mcmtr)) { |
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skx_printk(KERN_ERR, "ECC is disabled on imc %d\n", imc->mc); |
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return -ENODEV; |
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} |
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} |
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|
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return 0; |
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} |
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|
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#define SKX_MAX_SAD 24 |
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|
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#define SKX_GET_SAD(d, i, reg) \ |
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pci_read_config_dword((d)->sad_all, 0x60 + 8 * (i), &(reg)) |
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#define SKX_GET_ILV(d, i, reg) \ |
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pci_read_config_dword((d)->sad_all, 0x64 + 8 * (i), &(reg)) |
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#define SKX_SAD_MOD3MODE(sad) GET_BITFIELD((sad), 30, 31) |
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#define SKX_SAD_MOD3(sad) GET_BITFIELD((sad), 27, 27) |
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#define SKX_SAD_LIMIT(sad) (((u64)GET_BITFIELD((sad), 7, 26) << 26) | MASK26) |
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#define SKX_SAD_MOD3ASMOD2(sad) GET_BITFIELD((sad), 5, 6) |
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#define SKX_SAD_ATTR(sad) GET_BITFIELD((sad), 3, 4) |
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#define SKX_SAD_INTERLEAVE(sad) GET_BITFIELD((sad), 1, 2) |
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#define SKX_SAD_ENABLE(sad) GET_BITFIELD((sad), 0, 0) |
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#define SKX_ILV_REMOTE(tgt) (((tgt) & 8) == 0) |
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#define SKX_ILV_TARGET(tgt) ((tgt) & 7) |
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static void skx_show_retry_rd_err_log(struct decoded_addr *res, |
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char *msg, int len) |
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{ |
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u32 log0, log1, log2, log3, log4; |
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u32 corr0, corr1, corr2, corr3; |
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struct pci_dev *edev; |
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int n; |
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edev = res->dev->imc[res->imc].chan[res->channel].edev; |
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pci_read_config_dword(edev, 0x154, &log0); |
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pci_read_config_dword(edev, 0x148, &log1); |
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pci_read_config_dword(edev, 0x150, &log2); |
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pci_read_config_dword(edev, 0x15c, &log3); |
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pci_read_config_dword(edev, 0x114, &log4); |
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n = snprintf(msg, len, " retry_rd_err_log[%.8x %.8x %.8x %.8x %.8x]", |
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log0, log1, log2, log3, log4); |
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pci_read_config_dword(edev, 0x104, &corr0); |
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pci_read_config_dword(edev, 0x108, &corr1); |
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pci_read_config_dword(edev, 0x10c, &corr2); |
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pci_read_config_dword(edev, 0x110, &corr3); |
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if (len - n > 0) |
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snprintf(msg + n, len - n, |
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" correrrcnt[%.4x %.4x %.4x %.4x %.4x %.4x %.4x %.4x]", |
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corr0 & 0xffff, corr0 >> 16, |
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corr1 & 0xffff, corr1 >> 16, |
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corr2 & 0xffff, corr2 >> 16, |
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corr3 & 0xffff, corr3 >> 16); |
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} |
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static bool skx_sad_decode(struct decoded_addr *res) |
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{ |
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struct skx_dev *d = list_first_entry(skx_edac_list, typeof(*d), list); |
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u64 addr = res->addr; |
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int i, idx, tgt, lchan, shift; |
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u32 sad, ilv; |
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u64 limit, prev_limit; |
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int remote = 0; |
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|
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/* Simple sanity check for I/O space or out of range */ |
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if (addr >= skx_tohm || (addr >= skx_tolm && addr < BIT_ULL(32))) { |
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edac_dbg(0, "Address 0x%llx out of range\n", addr); |
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return false; |
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} |
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restart: |
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prev_limit = 0; |
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for (i = 0; i < SKX_MAX_SAD; i++) { |
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SKX_GET_SAD(d, i, sad); |
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limit = SKX_SAD_LIMIT(sad); |
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if (SKX_SAD_ENABLE(sad)) { |
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if (addr >= prev_limit && addr <= limit) |
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goto sad_found; |
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} |
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prev_limit = limit + 1; |
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} |
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edac_dbg(0, "No SAD entry for 0x%llx\n", addr); |
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return false; |
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sad_found: |
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SKX_GET_ILV(d, i, ilv); |
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|
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switch (SKX_SAD_INTERLEAVE(sad)) { |
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case 0: |
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idx = GET_BITFIELD(addr, 6, 8); |
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break; |
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case 1: |
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idx = GET_BITFIELD(addr, 8, 10); |
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break; |
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case 2: |
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idx = GET_BITFIELD(addr, 12, 14); |
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break; |
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case 3: |
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idx = GET_BITFIELD(addr, 30, 32); |
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break; |
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} |
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|
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tgt = GET_BITFIELD(ilv, 4 * idx, 4 * idx + 3); |
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|
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/* If point to another node, find it and start over */ |
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if (SKX_ILV_REMOTE(tgt)) { |
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if (remote) { |
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edac_dbg(0, "Double remote!\n"); |
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return false; |
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} |
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remote = 1; |
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list_for_each_entry(d, skx_edac_list, list) { |
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if (d->imc[0].src_id == SKX_ILV_TARGET(tgt)) |
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goto restart; |
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} |
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edac_dbg(0, "Can't find node %d\n", SKX_ILV_TARGET(tgt)); |
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return false; |
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} |
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|
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if (SKX_SAD_MOD3(sad) == 0) { |
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lchan = SKX_ILV_TARGET(tgt); |
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} else { |
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switch (SKX_SAD_MOD3MODE(sad)) { |
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case 0: |
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shift = 6; |
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break; |
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case 1: |
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shift = 8; |
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break; |
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case 2: |
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shift = 12; |
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break; |
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default: |
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edac_dbg(0, "illegal mod3mode\n"); |
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return false; |
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} |
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switch (SKX_SAD_MOD3ASMOD2(sad)) { |
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case 0: |
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lchan = (addr >> shift) % 3; |
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break; |
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case 1: |
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lchan = (addr >> shift) % 2; |
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break; |
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case 2: |
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lchan = (addr >> shift) % 2; |
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lchan = (lchan << 1) | !lchan; |
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break; |
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case 3: |
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lchan = ((addr >> shift) % 2) << 1; |
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break; |
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} |
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lchan = (lchan << 1) | (SKX_ILV_TARGET(tgt) & 1); |
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} |
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|
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res->dev = d; |
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res->socket = d->imc[0].src_id; |
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res->imc = GET_BITFIELD(d->mcroute, lchan * 3, lchan * 3 + 2); |
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res->channel = GET_BITFIELD(d->mcroute, lchan * 2 + 18, lchan * 2 + 19); |
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|
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edac_dbg(2, "0x%llx: socket=%d imc=%d channel=%d\n", |
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res->addr, res->socket, res->imc, res->channel); |
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return true; |
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} |
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|
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#define SKX_MAX_TAD 8 |
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|
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#define SKX_GET_TADBASE(d, mc, i, reg) \ |
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pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x850 + 4 * (i), &(reg)) |
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#define SKX_GET_TADWAYNESS(d, mc, i, reg) \ |
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pci_read_config_dword((d)->imc[mc].chan[0].cdev, 0x880 + 4 * (i), &(reg)) |
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#define SKX_GET_TADCHNILVOFFSET(d, mc, ch, i, reg) \ |
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pci_read_config_dword((d)->imc[mc].chan[ch].cdev, 0x90 + 4 * (i), &(reg)) |
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|
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#define SKX_TAD_BASE(b) ((u64)GET_BITFIELD((b), 12, 31) << 26) |
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#define SKX_TAD_SKT_GRAN(b) GET_BITFIELD((b), 4, 5) |
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#define SKX_TAD_CHN_GRAN(b) GET_BITFIELD((b), 6, 7) |
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#define SKX_TAD_LIMIT(b) (((u64)GET_BITFIELD((b), 12, 31) << 26) | MASK26) |
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#define SKX_TAD_OFFSET(b) ((u64)GET_BITFIELD((b), 4, 23) << 26) |
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#define SKX_TAD_SKTWAYS(b) (1 << GET_BITFIELD((b), 10, 11)) |
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#define SKX_TAD_CHNWAYS(b) (GET_BITFIELD((b), 8, 9) + 1) |
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|
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/* which bit used for both socket and channel interleave */ |
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static int skx_granularity[] = { 6, 8, 12, 30 }; |
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|
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static u64 skx_do_interleave(u64 addr, int shift, int ways, u64 lowbits) |
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{ |
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addr >>= shift; |
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addr /= ways; |
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addr <<= shift; |
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|
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return addr | (lowbits & ((1ull << shift) - 1)); |
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} |
|
|
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static bool skx_tad_decode(struct decoded_addr *res) |
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{ |
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int i; |
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u32 base, wayness, chnilvoffset; |
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int skt_interleave_bit, chn_interleave_bit; |
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u64 channel_addr; |
|
|
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for (i = 0; i < SKX_MAX_TAD; i++) { |
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SKX_GET_TADBASE(res->dev, res->imc, i, base); |
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SKX_GET_TADWAYNESS(res->dev, res->imc, i, wayness); |
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if (SKX_TAD_BASE(base) <= res->addr && res->addr <= SKX_TAD_LIMIT(wayness)) |
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goto tad_found; |
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} |
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edac_dbg(0, "No TAD entry for 0x%llx\n", res->addr); |
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return false; |
|
|
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tad_found: |
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res->sktways = SKX_TAD_SKTWAYS(wayness); |
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res->chanways = SKX_TAD_CHNWAYS(wayness); |
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skt_interleave_bit = skx_granularity[SKX_TAD_SKT_GRAN(base)]; |
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chn_interleave_bit = skx_granularity[SKX_TAD_CHN_GRAN(base)]; |
|
|
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SKX_GET_TADCHNILVOFFSET(res->dev, res->imc, res->channel, i, chnilvoffset); |
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channel_addr = res->addr - SKX_TAD_OFFSET(chnilvoffset); |
|
|
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if (res->chanways == 3 && skt_interleave_bit > chn_interleave_bit) { |
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/* Must handle channel first, then socket */ |
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channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit, |
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res->chanways, channel_addr); |
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channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit, |
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res->sktways, channel_addr); |
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} else { |
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/* Handle socket then channel. Preserve low bits from original address */ |
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channel_addr = skx_do_interleave(channel_addr, skt_interleave_bit, |
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res->sktways, res->addr); |
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channel_addr = skx_do_interleave(channel_addr, chn_interleave_bit, |
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res->chanways, res->addr); |
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} |
|
|
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res->chan_addr = channel_addr; |
|
|
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edac_dbg(2, "0x%llx: chan_addr=0x%llx sktways=%d chanways=%d\n", |
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res->addr, res->chan_addr, res->sktways, res->chanways); |
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return true; |
|
} |
|
|
|
#define SKX_MAX_RIR 4 |
|
|
|
#define SKX_GET_RIRWAYNESS(d, mc, ch, i, reg) \ |
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pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \ |
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0x108 + 4 * (i), &(reg)) |
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#define SKX_GET_RIRILV(d, mc, ch, idx, i, reg) \ |
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pci_read_config_dword((d)->imc[mc].chan[ch].cdev, \ |
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0x120 + 16 * (idx) + 4 * (i), &(reg)) |
|
|
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#define SKX_RIR_VALID(b) GET_BITFIELD((b), 31, 31) |
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#define SKX_RIR_LIMIT(b) (((u64)GET_BITFIELD((b), 1, 11) << 29) | MASK29) |
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#define SKX_RIR_WAYS(b) (1 << GET_BITFIELD((b), 28, 29)) |
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#define SKX_RIR_CHAN_RANK(b) GET_BITFIELD((b), 16, 19) |
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#define SKX_RIR_OFFSET(b) ((u64)(GET_BITFIELD((b), 2, 15) << 26)) |
|
|
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static bool skx_rir_decode(struct decoded_addr *res) |
|
{ |
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int i, idx, chan_rank; |
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int shift; |
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u32 rirway, rirlv; |
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u64 rank_addr, prev_limit = 0, limit; |
|
|
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if (res->dev->imc[res->imc].chan[res->channel].dimms[0].close_pg) |
|
shift = 6; |
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else |
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shift = 13; |
|
|
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for (i = 0; i < SKX_MAX_RIR; i++) { |
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SKX_GET_RIRWAYNESS(res->dev, res->imc, res->channel, i, rirway); |
|
limit = SKX_RIR_LIMIT(rirway); |
|
if (SKX_RIR_VALID(rirway)) { |
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if (prev_limit <= res->chan_addr && |
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res->chan_addr <= limit) |
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goto rir_found; |
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} |
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prev_limit = limit; |
|
} |
|
edac_dbg(0, "No RIR entry for 0x%llx\n", res->addr); |
|
return false; |
|
|
|
rir_found: |
|
rank_addr = res->chan_addr >> shift; |
|
rank_addr /= SKX_RIR_WAYS(rirway); |
|
rank_addr <<= shift; |
|
rank_addr |= res->chan_addr & GENMASK_ULL(shift - 1, 0); |
|
|
|
res->rank_address = rank_addr; |
|
idx = (res->chan_addr >> shift) % SKX_RIR_WAYS(rirway); |
|
|
|
SKX_GET_RIRILV(res->dev, res->imc, res->channel, idx, i, rirlv); |
|
res->rank_address = rank_addr - SKX_RIR_OFFSET(rirlv); |
|
chan_rank = SKX_RIR_CHAN_RANK(rirlv); |
|
res->channel_rank = chan_rank; |
|
res->dimm = chan_rank / 4; |
|
res->rank = chan_rank % 4; |
|
|
|
edac_dbg(2, "0x%llx: dimm=%d rank=%d chan_rank=%d rank_addr=0x%llx\n", |
|
res->addr, res->dimm, res->rank, |
|
res->channel_rank, res->rank_address); |
|
return true; |
|
} |
|
|
|
static u8 skx_close_row[] = { |
|
15, 16, 17, 18, 20, 21, 22, 28, 10, 11, 12, 13, 29, 30, 31, 32, 33 |
|
}; |
|
|
|
static u8 skx_close_column[] = { |
|
3, 4, 5, 14, 19, 23, 24, 25, 26, 27 |
|
}; |
|
|
|
static u8 skx_open_row[] = { |
|
14, 15, 16, 20, 28, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33 |
|
}; |
|
|
|
static u8 skx_open_column[] = { |
|
3, 4, 5, 6, 7, 8, 9, 10, 11, 12 |
|
}; |
|
|
|
static u8 skx_open_fine_column[] = { |
|
3, 4, 5, 7, 8, 9, 10, 11, 12, 13 |
|
}; |
|
|
|
static int skx_bits(u64 addr, int nbits, u8 *bits) |
|
{ |
|
int i, res = 0; |
|
|
|
for (i = 0; i < nbits; i++) |
|
res |= ((addr >> bits[i]) & 1) << i; |
|
return res; |
|
} |
|
|
|
static int skx_bank_bits(u64 addr, int b0, int b1, int do_xor, int x0, int x1) |
|
{ |
|
int ret = GET_BITFIELD(addr, b0, b0) | (GET_BITFIELD(addr, b1, b1) << 1); |
|
|
|
if (do_xor) |
|
ret ^= GET_BITFIELD(addr, x0, x0) | (GET_BITFIELD(addr, x1, x1) << 1); |
|
|
|
return ret; |
|
} |
|
|
|
static bool skx_mad_decode(struct decoded_addr *r) |
|
{ |
|
struct skx_dimm *dimm = &r->dev->imc[r->imc].chan[r->channel].dimms[r->dimm]; |
|
int bg0 = dimm->fine_grain_bank ? 6 : 13; |
|
|
|
if (dimm->close_pg) { |
|
r->row = skx_bits(r->rank_address, dimm->rowbits, skx_close_row); |
|
r->column = skx_bits(r->rank_address, dimm->colbits, skx_close_column); |
|
r->column |= 0x400; /* C10 is autoprecharge, always set */ |
|
r->bank_address = skx_bank_bits(r->rank_address, 8, 9, dimm->bank_xor_enable, 22, 28); |
|
r->bank_group = skx_bank_bits(r->rank_address, 6, 7, dimm->bank_xor_enable, 20, 21); |
|
} else { |
|
r->row = skx_bits(r->rank_address, dimm->rowbits, skx_open_row); |
|
if (dimm->fine_grain_bank) |
|
r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_fine_column); |
|
else |
|
r->column = skx_bits(r->rank_address, dimm->colbits, skx_open_column); |
|
r->bank_address = skx_bank_bits(r->rank_address, 18, 19, dimm->bank_xor_enable, 22, 23); |
|
r->bank_group = skx_bank_bits(r->rank_address, bg0, 17, dimm->bank_xor_enable, 20, 21); |
|
} |
|
r->row &= (1u << dimm->rowbits) - 1; |
|
|
|
edac_dbg(2, "0x%llx: row=0x%x col=0x%x bank_addr=%d bank_group=%d\n", |
|
r->addr, r->row, r->column, r->bank_address, |
|
r->bank_group); |
|
return true; |
|
} |
|
|
|
static bool skx_decode(struct decoded_addr *res) |
|
{ |
|
return skx_sad_decode(res) && skx_tad_decode(res) && |
|
skx_rir_decode(res) && skx_mad_decode(res); |
|
} |
|
|
|
static struct notifier_block skx_mce_dec = { |
|
.notifier_call = skx_mce_check_error, |
|
.priority = MCE_PRIO_EDAC, |
|
}; |
|
|
|
#ifdef CONFIG_EDAC_DEBUG |
|
/* |
|
* Debug feature. |
|
* Exercise the address decode logic by writing an address to |
|
* /sys/kernel/debug/edac/skx_test/addr. |
|
*/ |
|
static struct dentry *skx_test; |
|
|
|
static int debugfs_u64_set(void *data, u64 val) |
|
{ |
|
struct mce m; |
|
|
|
pr_warn_once("Fake error to 0x%llx injected via debugfs\n", val); |
|
|
|
memset(&m, 0, sizeof(m)); |
|
/* ADDRV + MemRd + Unknown channel */ |
|
m.status = MCI_STATUS_ADDRV + 0x90; |
|
/* One corrected error */ |
|
m.status |= BIT_ULL(MCI_STATUS_CEC_SHIFT); |
|
m.addr = val; |
|
skx_mce_check_error(NULL, 0, &m); |
|
|
|
return 0; |
|
} |
|
DEFINE_SIMPLE_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n"); |
|
|
|
static void setup_skx_debug(void) |
|
{ |
|
skx_test = edac_debugfs_create_dir("skx_test"); |
|
if (!skx_test) |
|
return; |
|
|
|
if (!edac_debugfs_create_file("addr", 0200, skx_test, |
|
NULL, &fops_u64_wo)) { |
|
debugfs_remove(skx_test); |
|
skx_test = NULL; |
|
} |
|
} |
|
|
|
static void teardown_skx_debug(void) |
|
{ |
|
debugfs_remove_recursive(skx_test); |
|
} |
|
#else |
|
static inline void setup_skx_debug(void) {} |
|
static inline void teardown_skx_debug(void) {} |
|
#endif /*CONFIG_EDAC_DEBUG*/ |
|
|
|
/* |
|
* skx_init: |
|
* make sure we are running on the correct cpu model |
|
* search for all the devices we need |
|
* check which DIMMs are present. |
|
*/ |
|
static int __init skx_init(void) |
|
{ |
|
const struct x86_cpu_id *id; |
|
struct res_config *cfg; |
|
const struct munit *m; |
|
const char *owner; |
|
int rc = 0, i, off[3] = {0xd0, 0xd4, 0xd8}; |
|
u8 mc = 0, src_id, node_id; |
|
struct skx_dev *d; |
|
|
|
edac_dbg(2, "\n"); |
|
|
|
owner = edac_get_owner(); |
|
if (owner && strncmp(owner, EDAC_MOD_STR, sizeof(EDAC_MOD_STR))) |
|
return -EBUSY; |
|
|
|
id = x86_match_cpu(skx_cpuids); |
|
if (!id) |
|
return -ENODEV; |
|
|
|
cfg = (struct res_config *)id->driver_data; |
|
|
|
rc = skx_get_hi_lo(0x2034, off, &skx_tolm, &skx_tohm); |
|
if (rc) |
|
return rc; |
|
|
|
rc = skx_get_all_bus_mappings(cfg, &skx_edac_list); |
|
if (rc < 0) |
|
goto fail; |
|
if (rc == 0) { |
|
edac_dbg(2, "No memory controllers found\n"); |
|
return -ENODEV; |
|
} |
|
skx_num_sockets = rc; |
|
|
|
for (m = skx_all_munits; m->did; m++) { |
|
rc = get_all_munits(m); |
|
if (rc < 0) |
|
goto fail; |
|
if (rc != m->per_socket * skx_num_sockets) { |
|
edac_dbg(2, "Expected %d, got %d of 0x%x\n", |
|
m->per_socket * skx_num_sockets, rc, m->did); |
|
rc = -ENODEV; |
|
goto fail; |
|
} |
|
} |
|
|
|
list_for_each_entry(d, skx_edac_list, list) { |
|
rc = skx_get_src_id(d, 0xf0, &src_id); |
|
if (rc < 0) |
|
goto fail; |
|
rc = skx_get_node_id(d, &node_id); |
|
if (rc < 0) |
|
goto fail; |
|
edac_dbg(2, "src_id=%d node_id=%d\n", src_id, node_id); |
|
for (i = 0; i < SKX_NUM_IMC; i++) { |
|
d->imc[i].mc = mc++; |
|
d->imc[i].lmc = i; |
|
d->imc[i].src_id = src_id; |
|
d->imc[i].node_id = node_id; |
|
rc = skx_register_mci(&d->imc[i], d->imc[i].chan[0].cdev, |
|
"Skylake Socket", EDAC_MOD_STR, |
|
skx_get_dimm_config, cfg); |
|
if (rc < 0) |
|
goto fail; |
|
} |
|
} |
|
|
|
skx_set_decode(skx_decode, skx_show_retry_rd_err_log); |
|
|
|
if (nvdimm_count && skx_adxl_get() == -ENODEV) |
|
skx_printk(KERN_NOTICE, "Only decoding DDR4 address!\n"); |
|
|
|
/* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
|
opstate_init(); |
|
|
|
setup_skx_debug(); |
|
|
|
mce_register_decode_chain(&skx_mce_dec); |
|
|
|
return 0; |
|
fail: |
|
skx_remove(); |
|
return rc; |
|
} |
|
|
|
static void __exit skx_exit(void) |
|
{ |
|
edac_dbg(2, "\n"); |
|
mce_unregister_decode_chain(&skx_mce_dec); |
|
teardown_skx_debug(); |
|
if (nvdimm_count) |
|
skx_adxl_put(); |
|
skx_remove(); |
|
} |
|
|
|
module_init(skx_init); |
|
module_exit(skx_exit); |
|
|
|
module_param(edac_op_state, int, 0444); |
|
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI"); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_AUTHOR("Tony Luck"); |
|
MODULE_DESCRIPTION("MC Driver for Intel Skylake server processors");
|
|
|