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599 lines
15 KiB
599 lines
15 KiB
/* |
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* Intel D82875P Memory Controller kernel module |
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* (C) 2003 Linux Networx (http://lnxi.com) |
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* This file may be distributed under the terms of the |
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* GNU General Public License. |
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* |
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* Written by Thayne Harbaugh |
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* Contributors: |
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* Wang Zhenyu at intel.com |
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* |
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* $Id: edac_i82875p.c,v 1.5.2.11 2005/10/05 00:43:44 dsp_llnl Exp $ |
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* |
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* Note: E7210 appears same as D82875P - zhenyu.z.wang at intel.com |
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*/ |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/pci.h> |
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#include <linux/pci_ids.h> |
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#include <linux/edac.h> |
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#include "edac_module.h" |
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#define EDAC_MOD_STR "i82875p_edac" |
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#define i82875p_printk(level, fmt, arg...) \ |
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edac_printk(level, "i82875p", fmt, ##arg) |
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#define i82875p_mc_printk(mci, level, fmt, arg...) \ |
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edac_mc_chipset_printk(mci, level, "i82875p", fmt, ##arg) |
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#ifndef PCI_DEVICE_ID_INTEL_82875_0 |
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#define PCI_DEVICE_ID_INTEL_82875_0 0x2578 |
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#endif /* PCI_DEVICE_ID_INTEL_82875_0 */ |
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#ifndef PCI_DEVICE_ID_INTEL_82875_6 |
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#define PCI_DEVICE_ID_INTEL_82875_6 0x257e |
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#endif /* PCI_DEVICE_ID_INTEL_82875_6 */ |
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/* four csrows in dual channel, eight in single channel */ |
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#define I82875P_NR_DIMMS 8 |
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#define I82875P_NR_CSROWS(nr_chans) (I82875P_NR_DIMMS / (nr_chans)) |
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|
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/* Intel 82875p register addresses - device 0 function 0 - DRAM Controller */ |
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#define I82875P_EAP 0x58 /* Error Address Pointer (32b) |
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* |
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* 31:12 block address |
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* 11:0 reserved |
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*/ |
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#define I82875P_DERRSYN 0x5c /* DRAM Error Syndrome (8b) |
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* |
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* 7:0 DRAM ECC Syndrome |
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*/ |
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#define I82875P_DES 0x5d /* DRAM Error Status (8b) |
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* |
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* 7:1 reserved |
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* 0 Error channel 0/1 |
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*/ |
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|
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#define I82875P_ERRSTS 0xc8 /* Error Status Register (16b) |
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* |
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* 15:10 reserved |
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* 9 non-DRAM lock error (ndlock) |
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* 8 Sftwr Generated SMI |
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* 7 ECC UE |
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* 6 reserved |
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* 5 MCH detects unimplemented cycle |
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* 4 AGP access outside GA |
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* 3 Invalid AGP access |
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* 2 Invalid GA translation table |
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* 1 Unsupported AGP command |
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* 0 ECC CE |
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*/ |
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#define I82875P_ERRCMD 0xca /* Error Command (16b) |
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* |
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* 15:10 reserved |
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* 9 SERR on non-DRAM lock |
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* 8 SERR on ECC UE |
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* 7 SERR on ECC CE |
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* 6 target abort on high exception |
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* 5 detect unimplemented cyc |
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* 4 AGP access outside of GA |
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* 3 SERR on invalid AGP access |
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* 2 invalid translation table |
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* 1 SERR on unsupported AGP command |
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* 0 reserved |
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*/ |
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/* Intel 82875p register addresses - device 6 function 0 - DRAM Controller */ |
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#define I82875P_PCICMD6 0x04 /* PCI Command Register (16b) |
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* |
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* 15:10 reserved |
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* 9 fast back-to-back - ro 0 |
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* 8 SERR enable - ro 0 |
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* 7 addr/data stepping - ro 0 |
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* 6 parity err enable - ro 0 |
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* 5 VGA palette snoop - ro 0 |
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* 4 mem wr & invalidate - ro 0 |
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* 3 special cycle - ro 0 |
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* 2 bus master - ro 0 |
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* 1 mem access dev6 - 0(dis),1(en) |
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* 0 IO access dev3 - 0(dis),1(en) |
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*/ |
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#define I82875P_BAR6 0x10 /* Mem Delays Base ADDR Reg (32b) |
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* |
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* 31:12 mem base addr [31:12] |
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* 11:4 address mask - ro 0 |
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* 3 prefetchable - ro 0(non),1(pre) |
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* 2:1 mem type - ro 0 |
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* 0 mem space - ro 0 |
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*/ |
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/* Intel 82875p MMIO register space - device 0 function 0 - MMR space */ |
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#define I82875P_DRB_SHIFT 26 /* 64MiB grain */ |
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#define I82875P_DRB 0x00 /* DRAM Row Boundary (8b x 8) |
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* |
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* 7 reserved |
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* 6:0 64MiB row boundary addr |
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*/ |
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#define I82875P_DRA 0x10 /* DRAM Row Attribute (4b x 8) |
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* |
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* 7 reserved |
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* 6:4 row attr row 1 |
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* 3 reserved |
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* 2:0 row attr row 0 |
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* |
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* 000 = 4KiB |
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* 001 = 8KiB |
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* 010 = 16KiB |
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* 011 = 32KiB |
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*/ |
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#define I82875P_DRC 0x68 /* DRAM Controller Mode (32b) |
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* |
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* 31:30 reserved |
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* 29 init complete |
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* 28:23 reserved |
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* 22:21 nr chan 00=1,01=2 |
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* 20 reserved |
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* 19:18 Data Integ Mode 00=none,01=ecc |
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* 17:11 reserved |
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* 10:8 refresh mode |
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* 7 reserved |
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* 6:4 mode select |
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* 3:2 reserved |
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* 1:0 DRAM type 01=DDR |
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*/ |
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enum i82875p_chips { |
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I82875P = 0, |
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}; |
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struct i82875p_pvt { |
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struct pci_dev *ovrfl_pdev; |
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void __iomem *ovrfl_window; |
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}; |
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struct i82875p_dev_info { |
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const char *ctl_name; |
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}; |
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struct i82875p_error_info { |
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u16 errsts; |
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u32 eap; |
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u8 des; |
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u8 derrsyn; |
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u16 errsts2; |
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}; |
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static const struct i82875p_dev_info i82875p_devs[] = { |
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[I82875P] = { |
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.ctl_name = "i82875p"}, |
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}; |
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static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has |
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* already registered driver |
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*/ |
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static struct edac_pci_ctl_info *i82875p_pci; |
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static void i82875p_get_error_info(struct mem_ctl_info *mci, |
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struct i82875p_error_info *info) |
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{ |
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struct pci_dev *pdev; |
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pdev = to_pci_dev(mci->pdev); |
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/* |
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* This is a mess because there is no atomic way to read all the |
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* registers at once and the registers can transition from CE being |
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* overwritten by UE. |
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*/ |
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pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts); |
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if (!(info->errsts & 0x0081)) |
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return; |
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pci_read_config_dword(pdev, I82875P_EAP, &info->eap); |
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pci_read_config_byte(pdev, I82875P_DES, &info->des); |
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pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn); |
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pci_read_config_word(pdev, I82875P_ERRSTS, &info->errsts2); |
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/* |
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* If the error is the same then we can for both reads then |
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* the first set of reads is valid. If there is a change then |
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* there is a CE no info and the second set of reads is valid |
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* and should be UE info. |
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*/ |
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if ((info->errsts ^ info->errsts2) & 0x0081) { |
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pci_read_config_dword(pdev, I82875P_EAP, &info->eap); |
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pci_read_config_byte(pdev, I82875P_DES, &info->des); |
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pci_read_config_byte(pdev, I82875P_DERRSYN, &info->derrsyn); |
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} |
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pci_write_bits16(pdev, I82875P_ERRSTS, 0x0081, 0x0081); |
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} |
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static int i82875p_process_error_info(struct mem_ctl_info *mci, |
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struct i82875p_error_info *info, |
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int handle_errors) |
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{ |
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int row, multi_chan; |
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multi_chan = mci->csrows[0]->nr_channels - 1; |
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if (!(info->errsts & 0x0081)) |
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return 0; |
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if (!handle_errors) |
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return 1; |
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if ((info->errsts ^ info->errsts2) & 0x0081) { |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, |
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-1, -1, -1, |
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"UE overwrote CE", ""); |
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info->errsts = info->errsts2; |
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} |
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info->eap >>= PAGE_SHIFT; |
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row = edac_mc_find_csrow_by_page(mci, info->eap); |
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if (info->errsts & 0x0080) |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
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info->eap, 0, 0, |
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row, -1, -1, |
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"i82875p UE", ""); |
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else |
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
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info->eap, 0, info->derrsyn, |
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row, multi_chan ? (info->des & 0x1) : 0, |
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-1, "i82875p CE", ""); |
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return 1; |
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} |
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static void i82875p_check(struct mem_ctl_info *mci) |
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{ |
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struct i82875p_error_info info; |
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i82875p_get_error_info(mci, &info); |
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i82875p_process_error_info(mci, &info, 1); |
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} |
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/* Return 0 on success or 1 on failure. */ |
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static int i82875p_setup_overfl_dev(struct pci_dev *pdev, |
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struct pci_dev **ovrfl_pdev, |
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void __iomem **ovrfl_window) |
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{ |
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struct pci_dev *dev; |
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void __iomem *window; |
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*ovrfl_pdev = NULL; |
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*ovrfl_window = NULL; |
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dev = pci_get_device(PCI_VEND_DEV(INTEL, 82875_6), NULL); |
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if (dev == NULL) { |
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/* Intel tells BIOS developers to hide device 6 which |
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* configures the overflow device access containing |
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* the DRBs - this is where we expose device 6. |
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* http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm |
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*/ |
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pci_write_bits8(pdev, 0xf4, 0x2, 0x2); |
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dev = pci_scan_single_device(pdev->bus, PCI_DEVFN(6, 0)); |
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if (dev == NULL) |
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return 1; |
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pci_bus_assign_resources(dev->bus); |
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pci_bus_add_device(dev); |
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} |
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*ovrfl_pdev = dev; |
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if (pci_enable_device(dev)) { |
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i82875p_printk(KERN_ERR, "%s(): Failed to enable overflow " |
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"device\n", __func__); |
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return 1; |
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} |
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if (pci_request_regions(dev, pci_name(dev))) { |
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#ifdef CORRECT_BIOS |
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goto fail0; |
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#endif |
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} |
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/* cache is irrelevant for PCI bus reads/writes */ |
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window = pci_ioremap_bar(dev, 0); |
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if (window == NULL) { |
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i82875p_printk(KERN_ERR, "%s(): Failed to ioremap bar6\n", |
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__func__); |
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goto fail1; |
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} |
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*ovrfl_window = window; |
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return 0; |
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fail1: |
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pci_release_regions(dev); |
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#ifdef CORRECT_BIOS |
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fail0: |
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pci_disable_device(dev); |
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#endif |
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/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */ |
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return 1; |
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} |
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/* Return 1 if dual channel mode is active. Else return 0. */ |
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static inline int dual_channel_active(u32 drc) |
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{ |
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return (drc >> 21) & 0x1; |
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} |
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static void i82875p_init_csrows(struct mem_ctl_info *mci, |
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struct pci_dev *pdev, |
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void __iomem * ovrfl_window, u32 drc) |
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{ |
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struct csrow_info *csrow; |
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struct dimm_info *dimm; |
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unsigned nr_chans = dual_channel_active(drc) + 1; |
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unsigned long last_cumul_size; |
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u8 value; |
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u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */ |
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u32 cumul_size, nr_pages; |
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int index, j; |
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drc_ddim = (drc >> 18) & 0x1; |
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last_cumul_size = 0; |
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/* The dram row boundary (DRB) reg values are boundary address |
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* for each DRAM row with a granularity of 32 or 64MB (single/dual |
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* channel operation). DRB regs are cumulative; therefore DRB7 will |
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* contain the total memory contained in all eight rows. |
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*/ |
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for (index = 0; index < mci->nr_csrows; index++) { |
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csrow = mci->csrows[index]; |
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value = readb(ovrfl_window + I82875P_DRB + index); |
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cumul_size = value << (I82875P_DRB_SHIFT - PAGE_SHIFT); |
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edac_dbg(3, "(%d) cumul_size 0x%x\n", index, cumul_size); |
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if (cumul_size == last_cumul_size) |
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continue; /* not populated */ |
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csrow->first_page = last_cumul_size; |
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csrow->last_page = cumul_size - 1; |
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nr_pages = cumul_size - last_cumul_size; |
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last_cumul_size = cumul_size; |
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for (j = 0; j < nr_chans; j++) { |
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dimm = csrow->channels[j]->dimm; |
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dimm->nr_pages = nr_pages / nr_chans; |
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dimm->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */ |
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dimm->mtype = MEM_DDR; |
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dimm->dtype = DEV_UNKNOWN; |
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dimm->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE; |
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} |
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} |
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} |
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static int i82875p_probe1(struct pci_dev *pdev, int dev_idx) |
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{ |
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int rc = -ENODEV; |
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struct mem_ctl_info *mci; |
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struct edac_mc_layer layers[2]; |
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struct i82875p_pvt *pvt; |
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struct pci_dev *ovrfl_pdev; |
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void __iomem *ovrfl_window; |
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u32 drc; |
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u32 nr_chans; |
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struct i82875p_error_info discard; |
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edac_dbg(0, "\n"); |
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if (i82875p_setup_overfl_dev(pdev, &ovrfl_pdev, &ovrfl_window)) |
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return -ENODEV; |
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drc = readl(ovrfl_window + I82875P_DRC); |
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nr_chans = dual_channel_active(drc) + 1; |
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
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layers[0].size = I82875P_NR_CSROWS(nr_chans); |
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layers[0].is_virt_csrow = true; |
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layers[1].type = EDAC_MC_LAYER_CHANNEL; |
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layers[1].size = nr_chans; |
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layers[1].is_virt_csrow = false; |
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt)); |
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if (!mci) { |
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rc = -ENOMEM; |
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goto fail0; |
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} |
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edac_dbg(3, "init mci\n"); |
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mci->pdev = &pdev->dev; |
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mci->mtype_cap = MEM_FLAG_DDR; |
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mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; |
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mci->edac_cap = EDAC_FLAG_UNKNOWN; |
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mci->mod_name = EDAC_MOD_STR; |
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mci->ctl_name = i82875p_devs[dev_idx].ctl_name; |
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mci->dev_name = pci_name(pdev); |
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mci->edac_check = i82875p_check; |
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mci->ctl_page_to_phys = NULL; |
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edac_dbg(3, "init pvt\n"); |
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pvt = (struct i82875p_pvt *)mci->pvt_info; |
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pvt->ovrfl_pdev = ovrfl_pdev; |
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pvt->ovrfl_window = ovrfl_window; |
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i82875p_init_csrows(mci, pdev, ovrfl_window, drc); |
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i82875p_get_error_info(mci, &discard); /* clear counters */ |
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|
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/* Here we assume that we will never see multiple instances of this |
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* type of memory controller. The ID is therefore hardcoded to 0. |
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*/ |
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if (edac_mc_add_mc(mci)) { |
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edac_dbg(3, "failed edac_mc_add_mc()\n"); |
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goto fail1; |
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} |
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/* allocating generic PCI control info */ |
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i82875p_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR); |
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if (!i82875p_pci) { |
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printk(KERN_WARNING |
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"%s(): Unable to create PCI control\n", |
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__func__); |
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printk(KERN_WARNING |
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"%s(): PCI error report via EDAC not setup\n", |
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__func__); |
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} |
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/* get this far and it's successful */ |
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edac_dbg(3, "success\n"); |
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return 0; |
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fail1: |
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edac_mc_free(mci); |
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fail0: |
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iounmap(ovrfl_window); |
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pci_release_regions(ovrfl_pdev); |
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pci_disable_device(ovrfl_pdev); |
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/* NOTE: the ovrfl proc entry and pci_dev are intentionally left */ |
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return rc; |
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} |
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/* returns count (>= 0), or negative on error */ |
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static int i82875p_init_one(struct pci_dev *pdev, |
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const struct pci_device_id *ent) |
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{ |
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int rc; |
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edac_dbg(0, "\n"); |
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i82875p_printk(KERN_INFO, "i82875p init one\n"); |
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if (pci_enable_device(pdev) < 0) |
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return -EIO; |
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rc = i82875p_probe1(pdev, ent->driver_data); |
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if (mci_pdev == NULL) |
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mci_pdev = pci_dev_get(pdev); |
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return rc; |
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} |
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static void i82875p_remove_one(struct pci_dev *pdev) |
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{ |
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struct mem_ctl_info *mci; |
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struct i82875p_pvt *pvt = NULL; |
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edac_dbg(0, "\n"); |
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if (i82875p_pci) |
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edac_pci_release_generic_ctl(i82875p_pci); |
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if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL) |
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return; |
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pvt = (struct i82875p_pvt *)mci->pvt_info; |
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if (pvt->ovrfl_window) |
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iounmap(pvt->ovrfl_window); |
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if (pvt->ovrfl_pdev) { |
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#ifdef CORRECT_BIOS |
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pci_release_regions(pvt->ovrfl_pdev); |
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#endif /*CORRECT_BIOS */ |
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pci_disable_device(pvt->ovrfl_pdev); |
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pci_dev_put(pvt->ovrfl_pdev); |
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} |
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edac_mc_free(mci); |
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} |
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static const struct pci_device_id i82875p_pci_tbl[] = { |
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{ |
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PCI_VEND_DEV(INTEL, 82875_0), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
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I82875P}, |
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{ |
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0, |
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} /* 0 terminated list. */ |
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}; |
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MODULE_DEVICE_TABLE(pci, i82875p_pci_tbl); |
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static struct pci_driver i82875p_driver = { |
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.name = EDAC_MOD_STR, |
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.probe = i82875p_init_one, |
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.remove = i82875p_remove_one, |
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.id_table = i82875p_pci_tbl, |
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}; |
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static int __init i82875p_init(void) |
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{ |
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int pci_rc; |
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edac_dbg(3, "\n"); |
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|
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/* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
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opstate_init(); |
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pci_rc = pci_register_driver(&i82875p_driver); |
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|
|
if (pci_rc < 0) |
|
goto fail0; |
|
|
|
if (mci_pdev == NULL) { |
|
mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
|
PCI_DEVICE_ID_INTEL_82875_0, NULL); |
|
|
|
if (!mci_pdev) { |
|
edac_dbg(0, "875p pci_get_device fail\n"); |
|
pci_rc = -ENODEV; |
|
goto fail1; |
|
} |
|
|
|
pci_rc = i82875p_init_one(mci_pdev, i82875p_pci_tbl); |
|
|
|
if (pci_rc < 0) { |
|
edac_dbg(0, "875p init fail\n"); |
|
pci_rc = -ENODEV; |
|
goto fail1; |
|
} |
|
} |
|
|
|
return 0; |
|
|
|
fail1: |
|
pci_unregister_driver(&i82875p_driver); |
|
|
|
fail0: |
|
pci_dev_put(mci_pdev); |
|
return pci_rc; |
|
} |
|
|
|
static void __exit i82875p_exit(void) |
|
{ |
|
edac_dbg(3, "\n"); |
|
|
|
i82875p_remove_one(mci_pdev); |
|
pci_dev_put(mci_pdev); |
|
|
|
pci_unregister_driver(&i82875p_driver); |
|
|
|
} |
|
|
|
module_init(i82875p_init); |
|
module_exit(i82875p_exit); |
|
|
|
MODULE_LICENSE("GPL"); |
|
MODULE_AUTHOR("Linux Networx (http://lnxi.com) Thayne Harbaugh"); |
|
MODULE_DESCRIPTION("MC support for Intel 82875 memory hub controllers"); |
|
|
|
module_param(edac_op_state, int, 0444); |
|
MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
|
|
|