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545 lines
13 KiB
545 lines
13 KiB
/* |
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* Intel 3200/3210 Memory Controller kernel module |
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* Copyright (C) 2008-2009 Akamai Technologies, Inc. |
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* Portions by Hitoshi Mitake <[email protected]>. |
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* |
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* This file may be distributed under the terms of the |
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* GNU General Public License. |
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*/ |
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#include <linux/module.h> |
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#include <linux/init.h> |
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#include <linux/pci.h> |
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#include <linux/pci_ids.h> |
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#include <linux/edac.h> |
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#include <linux/io.h> |
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#include "edac_module.h" |
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#include <linux/io-64-nonatomic-lo-hi.h> |
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#define EDAC_MOD_STR "i3200_edac" |
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#define PCI_DEVICE_ID_INTEL_3200_HB 0x29f0 |
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#define I3200_DIMMS 4 |
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#define I3200_RANKS 8 |
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#define I3200_RANKS_PER_CHANNEL 4 |
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#define I3200_CHANNELS 2 |
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|
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/* Intel 3200 register addresses - device 0 function 0 - DRAM Controller */ |
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#define I3200_MCHBAR_LOW 0x48 /* MCH Memory Mapped Register BAR */ |
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#define I3200_MCHBAR_HIGH 0x4c |
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#define I3200_MCHBAR_MASK 0xfffffc000ULL /* bits 35:14 */ |
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#define I3200_MMR_WINDOW_SIZE 16384 |
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#define I3200_TOM 0xa0 /* Top of Memory (16b) |
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* |
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* 15:10 reserved |
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* 9:0 total populated physical memory |
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*/ |
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#define I3200_TOM_MASK 0x3ff /* bits 9:0 */ |
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#define I3200_TOM_SHIFT 26 /* 64MiB grain */ |
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#define I3200_ERRSTS 0xc8 /* Error Status Register (16b) |
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* |
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* 15 reserved |
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* 14 Isochronous TBWRR Run Behind FIFO Full |
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* (ITCV) |
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* 13 Isochronous TBWRR Run Behind FIFO Put |
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* (ITSTV) |
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* 12 reserved |
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* 11 MCH Thermal Sensor Event |
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* for SMI/SCI/SERR (GTSE) |
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* 10 reserved |
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* 9 LOCK to non-DRAM Memory Flag (LCKF) |
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* 8 reserved |
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* 7 DRAM Throttle Flag (DTF) |
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* 6:2 reserved |
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* 1 Multi-bit DRAM ECC Error Flag (DMERR) |
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* 0 Single-bit DRAM ECC Error Flag (DSERR) |
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*/ |
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#define I3200_ERRSTS_UE 0x0002 |
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#define I3200_ERRSTS_CE 0x0001 |
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#define I3200_ERRSTS_BITS (I3200_ERRSTS_UE | I3200_ERRSTS_CE) |
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/* Intel MMIO register space - device 0 function 0 - MMR space */ |
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#define I3200_C0DRB 0x200 /* Channel 0 DRAM Rank Boundary (16b x 4) |
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* |
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* 15:10 reserved |
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* 9:0 Channel 0 DRAM Rank Boundary Address |
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*/ |
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#define I3200_C1DRB 0x600 /* Channel 1 DRAM Rank Boundary (16b x 4) */ |
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#define I3200_DRB_MASK 0x3ff /* bits 9:0 */ |
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#define I3200_DRB_SHIFT 26 /* 64MiB grain */ |
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#define I3200_C0ECCERRLOG 0x280 /* Channel 0 ECC Error Log (64b) |
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* |
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* 63:48 Error Column Address (ERRCOL) |
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* 47:32 Error Row Address (ERRROW) |
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* 31:29 Error Bank Address (ERRBANK) |
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* 28:27 Error Rank Address (ERRRANK) |
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* 26:24 reserved |
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* 23:16 Error Syndrome (ERRSYND) |
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* 15: 2 reserved |
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* 1 Multiple Bit Error Status (MERRSTS) |
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* 0 Correctable Error Status (CERRSTS) |
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*/ |
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#define I3200_C1ECCERRLOG 0x680 /* Chan 1 ECC Error Log (64b) */ |
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#define I3200_ECCERRLOG_CE 0x1 |
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#define I3200_ECCERRLOG_UE 0x2 |
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#define I3200_ECCERRLOG_RANK_BITS 0x18000000 |
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#define I3200_ECCERRLOG_RANK_SHIFT 27 |
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#define I3200_ECCERRLOG_SYNDROME_BITS 0xff0000 |
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#define I3200_ECCERRLOG_SYNDROME_SHIFT 16 |
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#define I3200_CAPID0 0xe0 /* P.95 of spec for details */ |
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struct i3200_priv { |
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void __iomem *window; |
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}; |
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static int nr_channels; |
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static int how_many_channels(struct pci_dev *pdev) |
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{ |
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int n_channels; |
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unsigned char capid0_8b; /* 8th byte of CAPID0 */ |
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pci_read_config_byte(pdev, I3200_CAPID0 + 8, &capid0_8b); |
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if (capid0_8b & 0x20) { /* check DCD: Dual Channel Disable */ |
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edac_dbg(0, "In single channel mode\n"); |
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n_channels = 1; |
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} else { |
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edac_dbg(0, "In dual channel mode\n"); |
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n_channels = 2; |
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} |
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if (capid0_8b & 0x10) /* check if both channels are filled */ |
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edac_dbg(0, "2 DIMMS per channel disabled\n"); |
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else |
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edac_dbg(0, "2 DIMMS per channel enabled\n"); |
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return n_channels; |
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} |
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static unsigned long eccerrlog_syndrome(u64 log) |
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{ |
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return (log & I3200_ECCERRLOG_SYNDROME_BITS) >> |
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I3200_ECCERRLOG_SYNDROME_SHIFT; |
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} |
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static int eccerrlog_row(int channel, u64 log) |
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{ |
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u64 rank = ((log & I3200_ECCERRLOG_RANK_BITS) >> |
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I3200_ECCERRLOG_RANK_SHIFT); |
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return rank | (channel * I3200_RANKS_PER_CHANNEL); |
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} |
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enum i3200_chips { |
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I3200 = 0, |
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}; |
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struct i3200_dev_info { |
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const char *ctl_name; |
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}; |
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struct i3200_error_info { |
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u16 errsts; |
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u16 errsts2; |
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u64 eccerrlog[I3200_CHANNELS]; |
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}; |
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static const struct i3200_dev_info i3200_devs[] = { |
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[I3200] = { |
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.ctl_name = "i3200" |
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}, |
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}; |
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static struct pci_dev *mci_pdev; |
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static int i3200_registered = 1; |
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static void i3200_clear_error_info(struct mem_ctl_info *mci) |
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{ |
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struct pci_dev *pdev; |
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pdev = to_pci_dev(mci->pdev); |
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/* |
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* Clear any error bits. |
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* (Yes, we really clear bits by writing 1 to them.) |
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*/ |
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pci_write_bits16(pdev, I3200_ERRSTS, I3200_ERRSTS_BITS, |
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I3200_ERRSTS_BITS); |
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} |
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static void i3200_get_and_clear_error_info(struct mem_ctl_info *mci, |
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struct i3200_error_info *info) |
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{ |
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struct pci_dev *pdev; |
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struct i3200_priv *priv = mci->pvt_info; |
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void __iomem *window = priv->window; |
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pdev = to_pci_dev(mci->pdev); |
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/* |
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* This is a mess because there is no atomic way to read all the |
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* registers at once and the registers can transition from CE being |
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* overwritten by UE. |
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*/ |
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pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts); |
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if (!(info->errsts & I3200_ERRSTS_BITS)) |
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return; |
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info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG); |
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if (nr_channels == 2) |
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info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG); |
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pci_read_config_word(pdev, I3200_ERRSTS, &info->errsts2); |
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/* |
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* If the error is the same for both reads then the first set |
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* of reads is valid. If there is a change then there is a CE |
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* with no info and the second set of reads is valid and |
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* should be UE info. |
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*/ |
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if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) { |
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info->eccerrlog[0] = readq(window + I3200_C0ECCERRLOG); |
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if (nr_channels == 2) |
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info->eccerrlog[1] = readq(window + I3200_C1ECCERRLOG); |
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} |
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i3200_clear_error_info(mci); |
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} |
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static void i3200_process_error_info(struct mem_ctl_info *mci, |
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struct i3200_error_info *info) |
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{ |
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int channel; |
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u64 log; |
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if (!(info->errsts & I3200_ERRSTS_BITS)) |
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return; |
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if ((info->errsts ^ info->errsts2) & I3200_ERRSTS_BITS) { |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0, |
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-1, -1, -1, "UE overwrote CE", ""); |
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info->errsts = info->errsts2; |
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} |
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for (channel = 0; channel < nr_channels; channel++) { |
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log = info->eccerrlog[channel]; |
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if (log & I3200_ECCERRLOG_UE) { |
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, |
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0, 0, 0, |
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eccerrlog_row(channel, log), |
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-1, -1, |
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"i3000 UE", ""); |
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} else if (log & I3200_ECCERRLOG_CE) { |
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, |
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0, 0, eccerrlog_syndrome(log), |
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eccerrlog_row(channel, log), |
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-1, -1, |
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"i3000 CE", ""); |
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} |
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} |
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} |
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static void i3200_check(struct mem_ctl_info *mci) |
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{ |
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struct i3200_error_info info; |
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i3200_get_and_clear_error_info(mci, &info); |
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i3200_process_error_info(mci, &info); |
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} |
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static void __iomem *i3200_map_mchbar(struct pci_dev *pdev) |
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{ |
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union { |
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u64 mchbar; |
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struct { |
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u32 mchbar_low; |
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u32 mchbar_high; |
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}; |
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} u; |
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void __iomem *window; |
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pci_read_config_dword(pdev, I3200_MCHBAR_LOW, &u.mchbar_low); |
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pci_read_config_dword(pdev, I3200_MCHBAR_HIGH, &u.mchbar_high); |
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u.mchbar &= I3200_MCHBAR_MASK; |
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if (u.mchbar != (resource_size_t)u.mchbar) { |
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printk(KERN_ERR |
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"i3200: mmio space beyond accessible range (0x%llx)\n", |
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(unsigned long long)u.mchbar); |
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return NULL; |
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} |
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window = ioremap(u.mchbar, I3200_MMR_WINDOW_SIZE); |
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if (!window) |
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printk(KERN_ERR "i3200: cannot map mmio space at 0x%llx\n", |
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(unsigned long long)u.mchbar); |
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return window; |
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} |
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static void i3200_get_drbs(void __iomem *window, |
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u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL]) |
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{ |
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int i; |
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for (i = 0; i < I3200_RANKS_PER_CHANNEL; i++) { |
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drbs[0][i] = readw(window + I3200_C0DRB + 2*i) & I3200_DRB_MASK; |
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drbs[1][i] = readw(window + I3200_C1DRB + 2*i) & I3200_DRB_MASK; |
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edac_dbg(0, "drb[0][%d] = %d, drb[1][%d] = %d\n", i, drbs[0][i], i, drbs[1][i]); |
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} |
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} |
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static bool i3200_is_stacked(struct pci_dev *pdev, |
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u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL]) |
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{ |
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u16 tom; |
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pci_read_config_word(pdev, I3200_TOM, &tom); |
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tom &= I3200_TOM_MASK; |
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return drbs[I3200_CHANNELS - 1][I3200_RANKS_PER_CHANNEL - 1] == tom; |
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} |
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static unsigned long drb_to_nr_pages( |
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u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL], bool stacked, |
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int channel, int rank) |
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{ |
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int n; |
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n = drbs[channel][rank]; |
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if (!n) |
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return 0; |
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if (rank > 0) |
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n -= drbs[channel][rank - 1]; |
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if (stacked && (channel == 1) && |
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drbs[channel][rank] == drbs[channel][I3200_RANKS_PER_CHANNEL - 1]) |
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n -= drbs[0][I3200_RANKS_PER_CHANNEL - 1]; |
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n <<= (I3200_DRB_SHIFT - PAGE_SHIFT); |
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return n; |
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} |
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static int i3200_probe1(struct pci_dev *pdev, int dev_idx) |
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{ |
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int rc; |
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int i, j; |
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struct mem_ctl_info *mci = NULL; |
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struct edac_mc_layer layers[2]; |
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u16 drbs[I3200_CHANNELS][I3200_RANKS_PER_CHANNEL]; |
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bool stacked; |
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void __iomem *window; |
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struct i3200_priv *priv; |
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edac_dbg(0, "MC:\n"); |
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window = i3200_map_mchbar(pdev); |
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if (!window) |
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return -ENODEV; |
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i3200_get_drbs(window, drbs); |
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nr_channels = how_many_channels(pdev); |
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; |
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layers[0].size = I3200_DIMMS; |
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layers[0].is_virt_csrow = true; |
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layers[1].type = EDAC_MC_LAYER_CHANNEL; |
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layers[1].size = nr_channels; |
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layers[1].is_virt_csrow = false; |
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, |
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sizeof(struct i3200_priv)); |
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if (!mci) |
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return -ENOMEM; |
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edac_dbg(3, "MC: init mci\n"); |
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mci->pdev = &pdev->dev; |
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mci->mtype_cap = MEM_FLAG_DDR2; |
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mci->edac_ctl_cap = EDAC_FLAG_SECDED; |
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mci->edac_cap = EDAC_FLAG_SECDED; |
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mci->mod_name = EDAC_MOD_STR; |
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mci->ctl_name = i3200_devs[dev_idx].ctl_name; |
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mci->dev_name = pci_name(pdev); |
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mci->edac_check = i3200_check; |
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mci->ctl_page_to_phys = NULL; |
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priv = mci->pvt_info; |
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priv->window = window; |
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stacked = i3200_is_stacked(pdev, drbs); |
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/* |
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* The dram rank boundary (DRB) reg values are boundary addresses |
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* for each DRAM rank with a granularity of 64MB. DRB regs are |
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* cumulative; the last one will contain the total memory |
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* contained in all ranks. |
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*/ |
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for (i = 0; i < I3200_DIMMS; i++) { |
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unsigned long nr_pages; |
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for (j = 0; j < nr_channels; j++) { |
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struct dimm_info *dimm = edac_get_dimm(mci, i, j, 0); |
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nr_pages = drb_to_nr_pages(drbs, stacked, j, i); |
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if (nr_pages == 0) |
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continue; |
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edac_dbg(0, "csrow %d, channel %d%s, size = %ld MiB\n", i, j, |
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stacked ? " (stacked)" : "", PAGES_TO_MiB(nr_pages)); |
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dimm->nr_pages = nr_pages; |
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dimm->grain = nr_pages << PAGE_SHIFT; |
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dimm->mtype = MEM_DDR2; |
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dimm->dtype = DEV_UNKNOWN; |
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dimm->edac_mode = EDAC_UNKNOWN; |
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} |
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} |
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i3200_clear_error_info(mci); |
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rc = -ENODEV; |
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if (edac_mc_add_mc(mci)) { |
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edac_dbg(3, "MC: failed edac_mc_add_mc()\n"); |
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goto fail; |
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} |
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/* get this far and it's successful */ |
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edac_dbg(3, "MC: success\n"); |
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return 0; |
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fail: |
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iounmap(window); |
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if (mci) |
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edac_mc_free(mci); |
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return rc; |
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} |
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static int i3200_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
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{ |
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int rc; |
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edac_dbg(0, "MC:\n"); |
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if (pci_enable_device(pdev) < 0) |
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return -EIO; |
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rc = i3200_probe1(pdev, ent->driver_data); |
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if (!mci_pdev) |
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mci_pdev = pci_dev_get(pdev); |
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return rc; |
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} |
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static void i3200_remove_one(struct pci_dev *pdev) |
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{ |
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struct mem_ctl_info *mci; |
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struct i3200_priv *priv; |
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edac_dbg(0, "\n"); |
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mci = edac_mc_del_mc(&pdev->dev); |
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if (!mci) |
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return; |
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priv = mci->pvt_info; |
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iounmap(priv->window); |
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edac_mc_free(mci); |
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pci_disable_device(pdev); |
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} |
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static const struct pci_device_id i3200_pci_tbl[] = { |
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{ |
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PCI_VEND_DEV(INTEL, 3200_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0, |
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I3200}, |
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{ |
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0, |
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} /* 0 terminated list. */ |
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}; |
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MODULE_DEVICE_TABLE(pci, i3200_pci_tbl); |
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static struct pci_driver i3200_driver = { |
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.name = EDAC_MOD_STR, |
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.probe = i3200_init_one, |
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.remove = i3200_remove_one, |
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.id_table = i3200_pci_tbl, |
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}; |
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static int __init i3200_init(void) |
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{ |
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int pci_rc; |
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edac_dbg(3, "MC:\n"); |
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/* Ensure that the OPSTATE is set correctly for POLL or NMI */ |
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opstate_init(); |
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pci_rc = pci_register_driver(&i3200_driver); |
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if (pci_rc < 0) |
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goto fail0; |
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if (!mci_pdev) { |
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i3200_registered = 0; |
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mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL, |
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PCI_DEVICE_ID_INTEL_3200_HB, NULL); |
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if (!mci_pdev) { |
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edac_dbg(0, "i3200 pci_get_device fail\n"); |
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pci_rc = -ENODEV; |
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goto fail1; |
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} |
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pci_rc = i3200_init_one(mci_pdev, i3200_pci_tbl); |
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if (pci_rc < 0) { |
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edac_dbg(0, "i3200 init fail\n"); |
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pci_rc = -ENODEV; |
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goto fail1; |
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} |
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} |
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return 0; |
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fail1: |
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pci_unregister_driver(&i3200_driver); |
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fail0: |
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pci_dev_put(mci_pdev); |
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return pci_rc; |
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} |
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static void __exit i3200_exit(void) |
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{ |
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edac_dbg(3, "MC:\n"); |
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pci_unregister_driver(&i3200_driver); |
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if (!i3200_registered) { |
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i3200_remove_one(mci_pdev); |
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pci_dev_put(mci_pdev); |
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} |
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} |
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module_init(i3200_init); |
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module_exit(i3200_exit); |
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MODULE_LICENSE("GPL"); |
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MODULE_AUTHOR("Akamai Technologies, Inc."); |
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MODULE_DESCRIPTION("MC support for Intel 3200 memory hub controllers"); |
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module_param(edac_op_state, int, 0444); |
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MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
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