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107 lines
3.1 KiB
107 lines
3.1 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* amd8131_edac.h, EDAC defs for AMD8131 hypertransport chip |
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* |
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* Copyright (c) 2008 Wind River Systems, Inc. |
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* |
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* Authors: Cao Qingtao <[email protected]> |
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* Benjamin Walsh <[email protected]> |
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* Hu Yongqi <[email protected]> |
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*/ |
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#ifndef _AMD8131_EDAC_H_ |
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#define _AMD8131_EDAC_H_ |
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#define DEVFN_PCIX_BRIDGE_NORTH_A 8 |
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#define DEVFN_PCIX_BRIDGE_NORTH_B 16 |
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#define DEVFN_PCIX_BRIDGE_SOUTH_A 24 |
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#define DEVFN_PCIX_BRIDGE_SOUTH_B 32 |
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/************************************************************ |
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* PCI-X Bridge Status and Command Register, DevA:0x04 |
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************************************************************/ |
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#define REG_STS_CMD 0x04 |
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enum sts_cmd_bits { |
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STS_CMD_SSE = BIT(30), |
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STS_CMD_SERREN = BIT(8) |
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}; |
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/************************************************************ |
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* PCI-X Bridge Interrupt and Bridge Control Register, |
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************************************************************/ |
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#define REG_INT_CTLR 0x3c |
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enum int_ctlr_bits { |
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INT_CTLR_DTSE = BIT(27), |
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INT_CTLR_DTS = BIT(26), |
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INT_CTLR_SERR = BIT(17), |
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INT_CTLR_PERR = BIT(16) |
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}; |
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/************************************************************ |
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* PCI-X Bridge Memory Base-Limit Register, DevA:0x1C |
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************************************************************/ |
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#define REG_MEM_LIM 0x1c |
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enum mem_limit_bits { |
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MEM_LIMIT_DPE = BIT(31), |
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MEM_LIMIT_RSE = BIT(30), |
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MEM_LIMIT_RMA = BIT(29), |
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MEM_LIMIT_RTA = BIT(28), |
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MEM_LIMIT_STA = BIT(27), |
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MEM_LIMIT_MDPE = BIT(24), |
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MEM_LIMIT_MASK = MEM_LIMIT_DPE|MEM_LIMIT_RSE|MEM_LIMIT_RMA| |
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MEM_LIMIT_RTA|MEM_LIMIT_STA|MEM_LIMIT_MDPE |
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}; |
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/************************************************************ |
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* Link Configuration And Control Register, side A |
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************************************************************/ |
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#define REG_LNK_CTRL_A 0xc4 |
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/************************************************************ |
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* Link Configuration And Control Register, side B |
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************************************************************/ |
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#define REG_LNK_CTRL_B 0xc8 |
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enum lnk_ctrl_bits { |
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LNK_CTRL_CRCERR_A = BIT(9), |
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LNK_CTRL_CRCERR_B = BIT(8), |
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LNK_CTRL_CRCFEN = BIT(1) |
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}; |
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enum pcix_bridge_inst { |
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NORTH_A = 0, |
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NORTH_B = 1, |
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SOUTH_A = 2, |
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SOUTH_B = 3, |
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NO_BRIDGE = 4 |
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}; |
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struct amd8131_dev_info { |
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int devfn; |
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enum pcix_bridge_inst inst; |
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struct pci_dev *dev; |
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int edac_idx; /* pci device index */ |
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char *ctl_name; |
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struct edac_pci_ctl_info *edac_dev; |
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}; |
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/* |
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* AMD8131 chipset has two pairs of PCIX Bridge and related IOAPIC |
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* Controller, and ATCA-6101 has two AMD8131 chipsets, so there are |
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* four PCIX Bridges on ATCA-6101 altogether. |
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* |
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* These PCIX Bridges share the same PCI Device ID and are all of |
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* Function Zero, they could be discrimated by their pci_dev->devfn. |
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* They share the same set of init/check/exit methods, and their |
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* private structures are collected in the devices[] array. |
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*/ |
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struct amd8131_info { |
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u16 err_dev; /* PCI Device ID for AMD8131 APIC*/ |
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struct amd8131_dev_info *devices; |
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void (*init)(struct amd8131_dev_info *dev_info); |
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void (*exit)(struct amd8131_dev_info *dev_info); |
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void (*check)(struct edac_pci_ctl_info *edac_dev); |
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}; |
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#endif /* _AMD8131_EDAC_H_ */ |
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