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541 lines
16 KiB
541 lines
16 KiB
# |
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# EDAC Kconfig |
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# Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com |
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# Licensed and distributed under the GPL |
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config EDAC_ATOMIC_SCRUB |
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bool |
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config EDAC_SUPPORT |
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bool |
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menuconfig EDAC |
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tristate "EDAC (Error Detection And Correction) reporting" |
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depends on HAS_IOMEM && EDAC_SUPPORT && RAS |
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help |
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EDAC is a subsystem along with hardware-specific drivers designed to |
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report hardware errors. These are low-level errors that are reported |
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in the CPU or supporting chipset or other subsystems: |
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memory errors, cache errors, PCI errors, thermal throttling, etc.. |
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If unsure, select 'Y'. |
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The mailing list for the EDAC project is [email protected]. |
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if EDAC |
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config EDAC_LEGACY_SYSFS |
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bool "EDAC legacy sysfs" |
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default y |
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help |
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Enable the compatibility sysfs nodes. |
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Use 'Y' if your edac utilities aren't ported to work with the newer |
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structures. |
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config EDAC_DEBUG |
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bool "Debugging" |
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select DEBUG_FS |
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help |
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This turns on debugging information for the entire EDAC subsystem. |
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You do so by inserting edac_module with "edac_debug_level=x." Valid |
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levels are 0-4 (from low to high) and by default it is set to 2. |
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Usually you should select 'N' here. |
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config EDAC_DECODE_MCE |
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tristate "Decode MCEs in human-readable form (only on AMD for now)" |
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depends on CPU_SUP_AMD && X86_MCE_AMD |
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default y |
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help |
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Enable this option if you want to decode Machine Check Exceptions |
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occurring on your machine in human-readable form. |
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You should definitely say Y here in case you want to decode MCEs |
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which occur really early upon boot, before the module infrastructure |
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has been initialized. |
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config EDAC_GHES |
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bool "Output ACPI APEI/GHES BIOS detected errors via EDAC" |
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depends on ACPI_APEI_GHES && (EDAC=y) |
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help |
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Not all machines support hardware-driven error report. Some of those |
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provide a BIOS-driven error report mechanism via ACPI, using the |
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APEI/GHES driver. By enabling this option, the error reports provided |
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by GHES are sent to userspace via the EDAC API. |
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When this option is enabled, it will disable the hardware-driven |
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mechanisms, if a GHES BIOS is detected, entering into the |
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"Firmware First" mode. |
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It should be noticed that keeping both GHES and a hardware-driven |
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error mechanism won't work well, as BIOS will race with OS, while |
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reading the error registers. So, if you want to not use "Firmware |
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first" GHES error mechanism, you should disable GHES either at |
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compilation time or by passing "ghes.disable=1" Kernel parameter |
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at boot time. |
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In doubt, say 'Y'. |
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config EDAC_AMD64 |
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tristate "AMD64 (Opteron, Athlon64)" |
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depends on AMD_NB && EDAC_DECODE_MCE |
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help |
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Support for error detection and correction of DRAM ECC errors on |
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the AMD64 families (>= K8) of memory controllers. |
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When EDAC_DEBUG is enabled, hardware error injection facilities |
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through sysfs are available: |
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AMD CPUs up to and excluding family 0x17 provide for Memory |
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Error Injection into the ECC detection circuits. The amd64_edac |
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module allows the operator/user to inject Uncorrectable and |
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Correctable errors into DRAM. |
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When enabled, in each of the respective memory controller directories |
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(/sys/devices/system/edac/mc/mcX), there are 3 input files: |
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- inject_section (0..3, 16-byte section of 64-byte cacheline), |
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- inject_word (0..8, 16-bit word of 16-byte section), |
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- inject_ecc_vector (hex ecc vector: select bits of inject word) |
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In addition, there are two control files, inject_read and inject_write, |
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which trigger the DRAM ECC Read and Write respectively. |
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config EDAC_AL_MC |
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tristate "Amazon's Annapurna Lab Memory Controller" |
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depends on (ARCH_ALPINE || COMPILE_TEST) |
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help |
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Support for error detection and correction for Amazon's Annapurna |
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Labs Alpine chips which allow 1 bit correction and 2 bits detection. |
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config EDAC_AMD76X |
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tristate "AMD 76x (760, 762, 768)" |
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depends on PCI && X86_32 |
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help |
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Support for error detection and correction on the AMD 76x |
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series of chipsets used with the Athlon processor. |
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config EDAC_E7XXX |
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tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" |
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depends on PCI && X86_32 |
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help |
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Support for error detection and correction on the Intel |
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E7205, E7500, E7501 and E7505 server chipsets. |
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config EDAC_E752X |
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tristate "Intel e752x (e7520, e7525, e7320) and 3100" |
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depends on PCI && X86 |
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help |
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Support for error detection and correction on the Intel |
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E7520, E7525, E7320 server chipsets. |
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config EDAC_I82443BXGX |
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tristate "Intel 82443BX/GX (440BX/GX)" |
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depends on PCI && X86_32 |
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depends on BROKEN |
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help |
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Support for error detection and correction on the Intel |
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82443BX/GX memory controllers (440BX/GX chipsets). |
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config EDAC_I82875P |
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tristate "Intel 82875p (D82875P, E7210)" |
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depends on PCI && X86_32 |
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help |
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Support for error detection and correction on the Intel |
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DP82785P and E7210 server chipsets. |
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config EDAC_I82975X |
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tristate "Intel 82975x (D82975x)" |
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depends on PCI && X86 |
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help |
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Support for error detection and correction on the Intel |
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DP82975x server chipsets. |
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config EDAC_I3000 |
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tristate "Intel 3000/3010" |
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depends on PCI && X86 |
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help |
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Support for error detection and correction on the Intel |
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3000 and 3010 server chipsets. |
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config EDAC_I3200 |
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tristate "Intel 3200" |
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depends on PCI && X86 |
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help |
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Support for error detection and correction on the Intel |
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3200 and 3210 server chipsets. |
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config EDAC_IE31200 |
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tristate "Intel e312xx" |
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depends on PCI && X86 |
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help |
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Support for error detection and correction on the Intel |
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E3-1200 based DRAM controllers. |
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config EDAC_X38 |
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tristate "Intel X38" |
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depends on PCI && X86 |
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help |
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Support for error detection and correction on the Intel |
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X38 server chipsets. |
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config EDAC_I5400 |
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tristate "Intel 5400 (Seaburg) chipsets" |
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depends on PCI && X86 |
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help |
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Support for error detection and correction the Intel |
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i5400 MCH chipset (Seaburg). |
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config EDAC_I7CORE |
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tristate "Intel i7 Core (Nehalem) processors" |
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depends on PCI && X86 && X86_MCE_INTEL |
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help |
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Support for error detection and correction the Intel |
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i7 Core (Nehalem) Integrated Memory Controller that exists on |
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newer processors like i7 Core, i7 Core Extreme, Xeon 35xx |
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and Xeon 55xx processors. |
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config EDAC_I82860 |
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tristate "Intel 82860" |
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depends on PCI && X86_32 |
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help |
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Support for error detection and correction on the Intel |
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82860 chipset. |
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config EDAC_R82600 |
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tristate "Radisys 82600 embedded chipset" |
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depends on PCI && X86_32 |
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help |
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Support for error detection and correction on the Radisys |
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82600 embedded chipset. |
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config EDAC_I5000 |
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tristate "Intel Greencreek/Blackford chipset" |
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depends on X86 && PCI |
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help |
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Support for error detection and correction the Intel |
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Greekcreek/Blackford chipsets. |
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config EDAC_I5100 |
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tristate "Intel San Clemente MCH" |
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depends on X86 && PCI |
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help |
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Support for error detection and correction the Intel |
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San Clemente MCH. |
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config EDAC_I7300 |
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tristate "Intel Clarksboro MCH" |
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depends on X86 && PCI |
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help |
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Support for error detection and correction the Intel |
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Clarksboro MCH (Intel 7300 chipset). |
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config EDAC_SBRIDGE |
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tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC" |
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depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG |
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help |
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Support for error detection and correction the Intel |
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Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers. |
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config EDAC_SKX |
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tristate "Intel Skylake server Integrated MC" |
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depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI |
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depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_SKX can't be y |
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select DMI |
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select ACPI_ADXL |
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help |
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Support for error detection and correction the Intel |
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Skylake server Integrated Memory Controllers. If your |
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system has non-volatile DIMMs you should also manually |
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select CONFIG_ACPI_NFIT. |
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config EDAC_I10NM |
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tristate "Intel 10nm server Integrated MC" |
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depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG && ACPI |
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depends on ACPI_NFIT || !ACPI_NFIT # if ACPI_NFIT=m, EDAC_I10NM can't be y |
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select DMI |
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select ACPI_ADXL |
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help |
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Support for error detection and correction the Intel |
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10nm server Integrated Memory Controllers. If your |
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system has non-volatile DIMMs you should also manually |
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select CONFIG_ACPI_NFIT. |
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config EDAC_PND2 |
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tristate "Intel Pondicherry2" |
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depends on PCI && X86_64 && X86_MCE_INTEL |
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help |
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Support for error detection and correction on the Intel |
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Pondicherry2 Integrated Memory Controller. This SoC IP is |
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first used on the Apollo Lake platform and Denverton |
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micro-server but may appear on others in the future. |
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config EDAC_IGEN6 |
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tristate "Intel client SoC Integrated MC" |
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depends on PCI && X86_64 && PCI_MMCONFIG && ARCH_HAVE_NMI_SAFE_CMPXCHG |
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help |
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Support for error detection and correction on the Intel |
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client SoC Integrated Memory Controller using In-Band ECC IP. |
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This In-Band ECC is first used on the Elkhart Lake SoC but |
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may appear on others in the future. |
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config EDAC_MPC85XX |
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bool "Freescale MPC83xx / MPC85xx" |
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depends on FSL_SOC && EDAC=y |
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help |
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Support for error detection and correction on the Freescale |
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MPC8349, MPC8560, MPC8540, MPC8548, T4240 |
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config EDAC_LAYERSCAPE |
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tristate "Freescale Layerscape DDR" |
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depends on ARCH_LAYERSCAPE || SOC_LS1021A |
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help |
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Support for error detection and correction on Freescale memory |
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controllers on Layerscape SoCs. |
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config EDAC_PASEMI |
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tristate "PA Semi PWRficient" |
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depends on PPC_PASEMI && PCI |
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help |
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Support for error detection and correction on PA Semi |
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PWRficient. |
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config EDAC_CELL |
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tristate "Cell Broadband Engine memory controller" |
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depends on PPC_CELL_COMMON |
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help |
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Support for error detection and correction on the |
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Cell Broadband Engine internal memory controller |
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on platform without a hypervisor |
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config EDAC_PPC4XX |
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tristate "PPC4xx IBM DDR2 Memory Controller" |
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depends on 4xx |
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help |
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This enables support for EDAC on the ECC memory used |
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with the IBM DDR2 memory controller found in various |
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PowerPC 4xx embedded processors such as the 405EX[r], |
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440SP, 440SPe, 460EX, 460GT and 460SX. |
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config EDAC_AMD8131 |
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tristate "AMD8131 HyperTransport PCI-X Tunnel" |
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depends on PCI && PPC_MAPLE |
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help |
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Support for error detection and correction on the |
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AMD8131 HyperTransport PCI-X Tunnel chip. |
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Note, add more Kconfig dependency if it's adopted |
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on some machine other than Maple. |
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config EDAC_AMD8111 |
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tristate "AMD8111 HyperTransport I/O Hub" |
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depends on PCI && PPC_MAPLE |
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help |
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Support for error detection and correction on the |
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AMD8111 HyperTransport I/O Hub chip. |
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Note, add more Kconfig dependency if it's adopted |
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on some machine other than Maple. |
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config EDAC_CPC925 |
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tristate "IBM CPC925 Memory Controller (PPC970FX)" |
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depends on PPC64 |
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help |
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Support for error detection and correction on the |
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IBM CPC925 Bridge and Memory Controller, which is |
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a companion chip to the PowerPC 970 family of |
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processors. |
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config EDAC_HIGHBANK_MC |
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tristate "Highbank Memory Controller" |
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depends on ARCH_HIGHBANK |
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help |
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Support for error detection and correction on the |
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Calxeda Highbank memory controller. |
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config EDAC_HIGHBANK_L2 |
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tristate "Highbank L2 Cache" |
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depends on ARCH_HIGHBANK |
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help |
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Support for error detection and correction on the |
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Calxeda Highbank memory controller. |
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config EDAC_OCTEON_PC |
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tristate "Cavium Octeon Primary Caches" |
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depends on CPU_CAVIUM_OCTEON |
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help |
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Support for error detection and correction on the primary caches of |
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the cnMIPS cores of Cavium Octeon family SOCs. |
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config EDAC_OCTEON_L2C |
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tristate "Cavium Octeon Secondary Caches (L2C)" |
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depends on CAVIUM_OCTEON_SOC |
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help |
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Support for error detection and correction on the |
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Cavium Octeon family of SOCs. |
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config EDAC_OCTEON_LMC |
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tristate "Cavium Octeon DRAM Memory Controller (LMC)" |
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depends on CAVIUM_OCTEON_SOC |
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help |
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Support for error detection and correction on the |
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Cavium Octeon family of SOCs. |
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config EDAC_OCTEON_PCI |
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tristate "Cavium Octeon PCI Controller" |
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depends on PCI && CAVIUM_OCTEON_SOC |
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help |
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Support for error detection and correction on the |
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Cavium Octeon family of SOCs. |
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config EDAC_THUNDERX |
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tristate "Cavium ThunderX EDAC" |
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depends on ARM64 |
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depends on PCI |
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help |
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Support for error detection and correction on the |
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Cavium ThunderX memory controllers (LMC), Cache |
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Coherent Processor Interconnect (CCPI) and L2 cache |
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blocks (TAD, CBC, MCI). |
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config EDAC_ALTERA |
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bool "Altera SOCFPGA ECC" |
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depends on EDAC=y && (ARCH_SOCFPGA || ARCH_STRATIX10) |
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help |
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Support for error detection and correction on the |
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Altera SOCs. This is the global enable for the |
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various Altera peripherals. |
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config EDAC_ALTERA_SDRAM |
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bool "Altera SDRAM ECC" |
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depends on EDAC_ALTERA=y |
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help |
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Support for error detection and correction on the |
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Altera SDRAM Memory for Altera SoCs. Note that the |
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preloader must initialize the SDRAM before loading |
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the kernel. |
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config EDAC_ALTERA_L2C |
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bool "Altera L2 Cache ECC" |
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depends on EDAC_ALTERA=y && CACHE_L2X0 |
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help |
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Support for error detection and correction on the |
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Altera L2 cache Memory for Altera SoCs. This option |
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requires L2 cache. |
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config EDAC_ALTERA_OCRAM |
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bool "Altera On-Chip RAM ECC" |
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depends on EDAC_ALTERA=y && SRAM && GENERIC_ALLOCATOR |
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help |
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Support for error detection and correction on the |
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Altera On-Chip RAM Memory for Altera SoCs. |
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config EDAC_ALTERA_ETHERNET |
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bool "Altera Ethernet FIFO ECC" |
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depends on EDAC_ALTERA=y |
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help |
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Support for error detection and correction on the |
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Altera Ethernet FIFO Memory for Altera SoCs. |
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config EDAC_ALTERA_NAND |
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bool "Altera NAND FIFO ECC" |
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depends on EDAC_ALTERA=y && MTD_NAND_DENALI |
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help |
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Support for error detection and correction on the |
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Altera NAND FIFO Memory for Altera SoCs. |
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config EDAC_ALTERA_DMA |
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bool "Altera DMA FIFO ECC" |
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depends on EDAC_ALTERA=y && PL330_DMA=y |
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help |
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Support for error detection and correction on the |
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Altera DMA FIFO Memory for Altera SoCs. |
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config EDAC_ALTERA_USB |
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bool "Altera USB FIFO ECC" |
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depends on EDAC_ALTERA=y && USB_DWC2 |
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help |
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Support for error detection and correction on the |
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Altera USB FIFO Memory for Altera SoCs. |
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config EDAC_ALTERA_QSPI |
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bool "Altera QSPI FIFO ECC" |
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depends on EDAC_ALTERA=y && SPI_CADENCE_QUADSPI |
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help |
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Support for error detection and correction on the |
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Altera QSPI FIFO Memory for Altera SoCs. |
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config EDAC_ALTERA_SDMMC |
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bool "Altera SDMMC FIFO ECC" |
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depends on EDAC_ALTERA=y && MMC_DW |
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help |
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Support for error detection and correction on the |
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Altera SDMMC FIFO Memory for Altera SoCs. |
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config EDAC_SIFIVE |
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bool "Sifive platform EDAC driver" |
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depends on EDAC=y && SIFIVE_L2 |
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help |
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Support for error detection and correction on the SiFive SoCs. |
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config EDAC_ARMADA_XP |
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bool "Marvell Armada XP DDR and L2 Cache ECC" |
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depends on MACH_MVEBU_V7 |
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help |
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Support for error correction and detection on the Marvell Aramada XP |
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DDR RAM and L2 cache controllers. |
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config EDAC_SYNOPSYS |
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tristate "Synopsys DDR Memory Controller" |
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depends on ARCH_ZYNQ || ARCH_ZYNQMP |
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help |
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Support for error detection and correction on the Synopsys DDR |
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memory controller. |
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config EDAC_XGENE |
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tristate "APM X-Gene SoC" |
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depends on (ARM64 || COMPILE_TEST) |
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help |
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Support for error detection and correction on the |
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APM X-Gene family of SOCs. |
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config EDAC_TI |
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tristate "Texas Instruments DDR3 ECC Controller" |
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depends on ARCH_KEYSTONE || SOC_DRA7XX |
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help |
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Support for error detection and correction on the TI SoCs. |
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config EDAC_QCOM |
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tristate "QCOM EDAC Controller" |
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depends on ARCH_QCOM && QCOM_LLCC |
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help |
|
Support for error detection and correction on the |
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Qualcomm Technologies, Inc. SoCs. |
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|
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This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs). |
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As of now, it supports error reporting for Last Level Cache Controller (LLCC) |
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of Tag RAM and Data RAM. |
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|
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For debugging issues having to do with stability and overall system |
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health, you should probably say 'Y' here. |
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config EDAC_ASPEED |
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tristate "Aspeed AST BMC SoC" |
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depends on ARCH_ASPEED |
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help |
|
Support for error detection and correction on the Aspeed AST BMC SoC. |
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|
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First, ECC must be configured in the bootloader. Then, this driver |
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will expose error counters via the EDAC kernel framework. |
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config EDAC_BLUEFIELD |
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tristate "Mellanox BlueField Memory ECC" |
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depends on ARM64 && ((MELLANOX_PLATFORM && ACPI) || COMPILE_TEST) |
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help |
|
Support for error detection and correction on the |
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Mellanox BlueField SoCs. |
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config EDAC_DMC520 |
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tristate "ARM DMC-520 ECC" |
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depends on ARM64 |
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help |
|
Support for error detection and correction on the |
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SoCs with ARM DMC-520 DRAM controller. |
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endif # EDAC
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