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681 lines
16 KiB
681 lines
16 KiB
/* |
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* MOXA ART SoCs DMA Engine support. |
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* |
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* Copyright (C) 2013 Jonas Jensen |
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* |
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* Jonas Jensen <[email protected]> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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|
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#include <linux/dmaengine.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/err.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/list.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_dma.h> |
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#include <linux/bitops.h> |
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#include <asm/cacheflush.h> |
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#include "dmaengine.h" |
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#include "virt-dma.h" |
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#define APB_DMA_MAX_CHANNEL 4 |
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#define REG_OFF_ADDRESS_SOURCE 0 |
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#define REG_OFF_ADDRESS_DEST 4 |
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#define REG_OFF_CYCLES 8 |
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#define REG_OFF_CTRL 12 |
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#define REG_OFF_CHAN_SIZE 16 |
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#define APB_DMA_ENABLE BIT(0) |
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#define APB_DMA_FIN_INT_STS BIT(1) |
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#define APB_DMA_FIN_INT_EN BIT(2) |
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#define APB_DMA_BURST_MODE BIT(3) |
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#define APB_DMA_ERR_INT_STS BIT(4) |
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#define APB_DMA_ERR_INT_EN BIT(5) |
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|
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/* |
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* Unset: APB |
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* Set: AHB |
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*/ |
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#define APB_DMA_SOURCE_SELECT 0x40 |
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#define APB_DMA_DEST_SELECT 0x80 |
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#define APB_DMA_SOURCE 0x100 |
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#define APB_DMA_DEST 0x1000 |
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#define APB_DMA_SOURCE_MASK 0x700 |
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#define APB_DMA_DEST_MASK 0x7000 |
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/* |
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* 000: No increment |
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* 001: +1 (Burst=0), +4 (Burst=1) |
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* 010: +2 (Burst=0), +8 (Burst=1) |
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* 011: +4 (Burst=0), +16 (Burst=1) |
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* 101: -1 (Burst=0), -4 (Burst=1) |
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* 110: -2 (Burst=0), -8 (Burst=1) |
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* 111: -4 (Burst=0), -16 (Burst=1) |
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*/ |
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#define APB_DMA_SOURCE_INC_0 0 |
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#define APB_DMA_SOURCE_INC_1_4 0x100 |
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#define APB_DMA_SOURCE_INC_2_8 0x200 |
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#define APB_DMA_SOURCE_INC_4_16 0x300 |
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#define APB_DMA_SOURCE_DEC_1_4 0x500 |
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#define APB_DMA_SOURCE_DEC_2_8 0x600 |
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#define APB_DMA_SOURCE_DEC_4_16 0x700 |
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#define APB_DMA_DEST_INC_0 0 |
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#define APB_DMA_DEST_INC_1_4 0x1000 |
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#define APB_DMA_DEST_INC_2_8 0x2000 |
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#define APB_DMA_DEST_INC_4_16 0x3000 |
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#define APB_DMA_DEST_DEC_1_4 0x5000 |
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#define APB_DMA_DEST_DEC_2_8 0x6000 |
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#define APB_DMA_DEST_DEC_4_16 0x7000 |
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/* |
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* Request signal select source/destination address for DMA hardware handshake. |
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* |
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* The request line number is a property of the DMA controller itself, |
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* e.g. MMC must always request channels where dma_slave_config->slave_id is 5. |
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* |
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* 0: No request / Grant signal |
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* 1-15: Request / Grant signal |
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*/ |
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#define APB_DMA_SOURCE_REQ_NO 0x1000000 |
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#define APB_DMA_SOURCE_REQ_NO_MASK 0xf000000 |
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#define APB_DMA_DEST_REQ_NO 0x10000 |
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#define APB_DMA_DEST_REQ_NO_MASK 0xf0000 |
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#define APB_DMA_DATA_WIDTH 0x100000 |
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#define APB_DMA_DATA_WIDTH_MASK 0x300000 |
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/* |
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* Data width of transfer: |
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* |
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* 00: Word |
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* 01: Half |
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* 10: Byte |
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*/ |
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#define APB_DMA_DATA_WIDTH_4 0 |
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#define APB_DMA_DATA_WIDTH_2 0x100000 |
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#define APB_DMA_DATA_WIDTH_1 0x200000 |
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#define APB_DMA_CYCLES_MASK 0x00ffffff |
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#define MOXART_DMA_DATA_TYPE_S8 0x00 |
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#define MOXART_DMA_DATA_TYPE_S16 0x01 |
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#define MOXART_DMA_DATA_TYPE_S32 0x02 |
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struct moxart_sg { |
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dma_addr_t addr; |
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uint32_t len; |
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}; |
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struct moxart_desc { |
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enum dma_transfer_direction dma_dir; |
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dma_addr_t dev_addr; |
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unsigned int sglen; |
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unsigned int dma_cycles; |
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struct virt_dma_desc vd; |
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uint8_t es; |
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struct moxart_sg sg[]; |
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}; |
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struct moxart_chan { |
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struct virt_dma_chan vc; |
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void __iomem *base; |
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struct moxart_desc *desc; |
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struct dma_slave_config cfg; |
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bool allocated; |
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bool error; |
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int ch_num; |
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unsigned int line_reqno; |
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unsigned int sgidx; |
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}; |
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struct moxart_dmadev { |
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struct dma_device dma_slave; |
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struct moxart_chan slave_chans[APB_DMA_MAX_CHANNEL]; |
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unsigned int irq; |
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}; |
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struct moxart_filter_data { |
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struct moxart_dmadev *mdc; |
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struct of_phandle_args *dma_spec; |
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}; |
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static const unsigned int es_bytes[] = { |
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[MOXART_DMA_DATA_TYPE_S8] = 1, |
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[MOXART_DMA_DATA_TYPE_S16] = 2, |
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[MOXART_DMA_DATA_TYPE_S32] = 4, |
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}; |
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static struct device *chan2dev(struct dma_chan *chan) |
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{ |
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return &chan->dev->device; |
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} |
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static inline struct moxart_chan *to_moxart_dma_chan(struct dma_chan *c) |
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{ |
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return container_of(c, struct moxart_chan, vc.chan); |
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} |
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static inline struct moxart_desc *to_moxart_dma_desc( |
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struct dma_async_tx_descriptor *t) |
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{ |
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return container_of(t, struct moxart_desc, vd.tx); |
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} |
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static void moxart_dma_desc_free(struct virt_dma_desc *vd) |
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{ |
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kfree(container_of(vd, struct moxart_desc, vd)); |
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} |
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static int moxart_terminate_all(struct dma_chan *chan) |
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{ |
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struct moxart_chan *ch = to_moxart_dma_chan(chan); |
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unsigned long flags; |
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LIST_HEAD(head); |
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u32 ctrl; |
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dev_dbg(chan2dev(chan), "%s: ch=%p\n", __func__, ch); |
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spin_lock_irqsave(&ch->vc.lock, flags); |
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if (ch->desc) { |
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moxart_dma_desc_free(&ch->desc->vd); |
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ch->desc = NULL; |
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} |
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ctrl = readl(ch->base + REG_OFF_CTRL); |
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ctrl &= ~(APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN); |
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writel(ctrl, ch->base + REG_OFF_CTRL); |
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vchan_get_all_descriptors(&ch->vc, &head); |
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spin_unlock_irqrestore(&ch->vc.lock, flags); |
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vchan_dma_desc_free_list(&ch->vc, &head); |
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return 0; |
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} |
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static int moxart_slave_config(struct dma_chan *chan, |
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struct dma_slave_config *cfg) |
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{ |
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struct moxart_chan *ch = to_moxart_dma_chan(chan); |
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u32 ctrl; |
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ch->cfg = *cfg; |
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ctrl = readl(ch->base + REG_OFF_CTRL); |
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ctrl |= APB_DMA_BURST_MODE; |
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ctrl &= ~(APB_DMA_DEST_MASK | APB_DMA_SOURCE_MASK); |
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ctrl &= ~(APB_DMA_DEST_REQ_NO_MASK | APB_DMA_SOURCE_REQ_NO_MASK); |
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switch (ch->cfg.src_addr_width) { |
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case DMA_SLAVE_BUSWIDTH_1_BYTE: |
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ctrl |= APB_DMA_DATA_WIDTH_1; |
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if (ch->cfg.direction != DMA_MEM_TO_DEV) |
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ctrl |= APB_DMA_DEST_INC_1_4; |
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else |
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ctrl |= APB_DMA_SOURCE_INC_1_4; |
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break; |
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case DMA_SLAVE_BUSWIDTH_2_BYTES: |
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ctrl |= APB_DMA_DATA_WIDTH_2; |
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if (ch->cfg.direction != DMA_MEM_TO_DEV) |
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ctrl |= APB_DMA_DEST_INC_2_8; |
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else |
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ctrl |= APB_DMA_SOURCE_INC_2_8; |
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break; |
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case DMA_SLAVE_BUSWIDTH_4_BYTES: |
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ctrl &= ~APB_DMA_DATA_WIDTH; |
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if (ch->cfg.direction != DMA_MEM_TO_DEV) |
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ctrl |= APB_DMA_DEST_INC_4_16; |
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else |
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ctrl |= APB_DMA_SOURCE_INC_4_16; |
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break; |
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default: |
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return -EINVAL; |
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} |
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if (ch->cfg.direction == DMA_MEM_TO_DEV) { |
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ctrl &= ~APB_DMA_DEST_SELECT; |
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ctrl |= APB_DMA_SOURCE_SELECT; |
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ctrl |= (ch->line_reqno << 16 & |
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APB_DMA_DEST_REQ_NO_MASK); |
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} else { |
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ctrl |= APB_DMA_DEST_SELECT; |
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ctrl &= ~APB_DMA_SOURCE_SELECT; |
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ctrl |= (ch->line_reqno << 24 & |
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APB_DMA_SOURCE_REQ_NO_MASK); |
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} |
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writel(ctrl, ch->base + REG_OFF_CTRL); |
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return 0; |
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} |
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static struct dma_async_tx_descriptor *moxart_prep_slave_sg( |
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struct dma_chan *chan, struct scatterlist *sgl, |
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unsigned int sg_len, enum dma_transfer_direction dir, |
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unsigned long tx_flags, void *context) |
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{ |
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struct moxart_chan *ch = to_moxart_dma_chan(chan); |
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struct moxart_desc *d; |
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enum dma_slave_buswidth dev_width; |
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dma_addr_t dev_addr; |
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struct scatterlist *sgent; |
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unsigned int es; |
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unsigned int i; |
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if (!is_slave_direction(dir)) { |
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dev_err(chan2dev(chan), "%s: invalid DMA direction\n", |
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__func__); |
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return NULL; |
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} |
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if (dir == DMA_DEV_TO_MEM) { |
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dev_addr = ch->cfg.src_addr; |
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dev_width = ch->cfg.src_addr_width; |
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} else { |
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dev_addr = ch->cfg.dst_addr; |
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dev_width = ch->cfg.dst_addr_width; |
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} |
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switch (dev_width) { |
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case DMA_SLAVE_BUSWIDTH_1_BYTE: |
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es = MOXART_DMA_DATA_TYPE_S8; |
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break; |
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case DMA_SLAVE_BUSWIDTH_2_BYTES: |
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es = MOXART_DMA_DATA_TYPE_S16; |
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break; |
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case DMA_SLAVE_BUSWIDTH_4_BYTES: |
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es = MOXART_DMA_DATA_TYPE_S32; |
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break; |
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default: |
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dev_err(chan2dev(chan), "%s: unsupported data width (%u)\n", |
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__func__, dev_width); |
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return NULL; |
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} |
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d = kzalloc(struct_size(d, sg, sg_len), GFP_ATOMIC); |
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if (!d) |
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return NULL; |
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d->dma_dir = dir; |
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d->dev_addr = dev_addr; |
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d->es = es; |
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for_each_sg(sgl, sgent, sg_len, i) { |
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d->sg[i].addr = sg_dma_address(sgent); |
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d->sg[i].len = sg_dma_len(sgent); |
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} |
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d->sglen = sg_len; |
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ch->error = 0; |
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return vchan_tx_prep(&ch->vc, &d->vd, tx_flags); |
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} |
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static struct dma_chan *moxart_of_xlate(struct of_phandle_args *dma_spec, |
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struct of_dma *ofdma) |
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{ |
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struct moxart_dmadev *mdc = ofdma->of_dma_data; |
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struct dma_chan *chan; |
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struct moxart_chan *ch; |
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chan = dma_get_any_slave_channel(&mdc->dma_slave); |
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if (!chan) |
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return NULL; |
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ch = to_moxart_dma_chan(chan); |
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ch->line_reqno = dma_spec->args[0]; |
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return chan; |
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} |
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static int moxart_alloc_chan_resources(struct dma_chan *chan) |
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{ |
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struct moxart_chan *ch = to_moxart_dma_chan(chan); |
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dev_dbg(chan2dev(chan), "%s: allocating channel #%u\n", |
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__func__, ch->ch_num); |
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ch->allocated = 1; |
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return 0; |
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} |
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static void moxart_free_chan_resources(struct dma_chan *chan) |
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{ |
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struct moxart_chan *ch = to_moxart_dma_chan(chan); |
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vchan_free_chan_resources(&ch->vc); |
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dev_dbg(chan2dev(chan), "%s: freeing channel #%u\n", |
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__func__, ch->ch_num); |
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ch->allocated = 0; |
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} |
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static void moxart_dma_set_params(struct moxart_chan *ch, dma_addr_t src_addr, |
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dma_addr_t dst_addr) |
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{ |
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writel(src_addr, ch->base + REG_OFF_ADDRESS_SOURCE); |
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writel(dst_addr, ch->base + REG_OFF_ADDRESS_DEST); |
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} |
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static void moxart_set_transfer_params(struct moxart_chan *ch, unsigned int len) |
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{ |
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struct moxart_desc *d = ch->desc; |
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unsigned int sglen_div = es_bytes[d->es]; |
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d->dma_cycles = len >> sglen_div; |
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/* |
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* There are 4 cycles on 64 bytes copied, i.e. one cycle copies 16 |
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* bytes ( when width is APB_DMAB_DATA_WIDTH_4 ). |
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*/ |
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writel(d->dma_cycles, ch->base + REG_OFF_CYCLES); |
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dev_dbg(chan2dev(&ch->vc.chan), "%s: set %u DMA cycles (len=%u)\n", |
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__func__, d->dma_cycles, len); |
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} |
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static void moxart_start_dma(struct moxart_chan *ch) |
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{ |
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u32 ctrl; |
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ctrl = readl(ch->base + REG_OFF_CTRL); |
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ctrl |= (APB_DMA_ENABLE | APB_DMA_FIN_INT_EN | APB_DMA_ERR_INT_EN); |
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writel(ctrl, ch->base + REG_OFF_CTRL); |
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} |
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static void moxart_dma_start_sg(struct moxart_chan *ch, unsigned int idx) |
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{ |
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struct moxart_desc *d = ch->desc; |
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struct moxart_sg *sg = ch->desc->sg + idx; |
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if (ch->desc->dma_dir == DMA_MEM_TO_DEV) |
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moxart_dma_set_params(ch, sg->addr, d->dev_addr); |
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else if (ch->desc->dma_dir == DMA_DEV_TO_MEM) |
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moxart_dma_set_params(ch, d->dev_addr, sg->addr); |
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moxart_set_transfer_params(ch, sg->len); |
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moxart_start_dma(ch); |
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} |
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static void moxart_dma_start_desc(struct dma_chan *chan) |
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{ |
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struct moxart_chan *ch = to_moxart_dma_chan(chan); |
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struct virt_dma_desc *vd; |
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vd = vchan_next_desc(&ch->vc); |
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if (!vd) { |
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ch->desc = NULL; |
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return; |
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} |
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list_del(&vd->node); |
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ch->desc = to_moxart_dma_desc(&vd->tx); |
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ch->sgidx = 0; |
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moxart_dma_start_sg(ch, 0); |
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} |
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static void moxart_issue_pending(struct dma_chan *chan) |
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{ |
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struct moxart_chan *ch = to_moxart_dma_chan(chan); |
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unsigned long flags; |
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spin_lock_irqsave(&ch->vc.lock, flags); |
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if (vchan_issue_pending(&ch->vc) && !ch->desc) |
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moxart_dma_start_desc(chan); |
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spin_unlock_irqrestore(&ch->vc.lock, flags); |
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} |
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static size_t moxart_dma_desc_size(struct moxart_desc *d, |
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unsigned int completed_sgs) |
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{ |
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unsigned int i; |
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size_t size; |
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for (size = i = completed_sgs; i < d->sglen; i++) |
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size += d->sg[i].len; |
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return size; |
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} |
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static size_t moxart_dma_desc_size_in_flight(struct moxart_chan *ch) |
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{ |
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size_t size; |
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unsigned int completed_cycles, cycles; |
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size = moxart_dma_desc_size(ch->desc, ch->sgidx); |
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cycles = readl(ch->base + REG_OFF_CYCLES); |
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completed_cycles = (ch->desc->dma_cycles - cycles); |
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size -= completed_cycles << es_bytes[ch->desc->es]; |
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dev_dbg(chan2dev(&ch->vc.chan), "%s: size=%zu\n", __func__, size); |
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return size; |
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} |
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static enum dma_status moxart_tx_status(struct dma_chan *chan, |
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dma_cookie_t cookie, |
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struct dma_tx_state *txstate) |
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{ |
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struct moxart_chan *ch = to_moxart_dma_chan(chan); |
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struct virt_dma_desc *vd; |
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struct moxart_desc *d; |
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enum dma_status ret; |
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unsigned long flags; |
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/* |
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* dma_cookie_status() assigns initial residue value. |
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*/ |
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ret = dma_cookie_status(chan, cookie, txstate); |
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spin_lock_irqsave(&ch->vc.lock, flags); |
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vd = vchan_find_desc(&ch->vc, cookie); |
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if (vd) { |
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d = to_moxart_dma_desc(&vd->tx); |
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txstate->residue = moxart_dma_desc_size(d, 0); |
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} else if (ch->desc && ch->desc->vd.tx.cookie == cookie) { |
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txstate->residue = moxart_dma_desc_size_in_flight(ch); |
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} |
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spin_unlock_irqrestore(&ch->vc.lock, flags); |
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if (ch->error) |
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return DMA_ERROR; |
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return ret; |
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} |
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static void moxart_dma_init(struct dma_device *dma, struct device *dev) |
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{ |
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dma->device_prep_slave_sg = moxart_prep_slave_sg; |
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dma->device_alloc_chan_resources = moxart_alloc_chan_resources; |
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dma->device_free_chan_resources = moxart_free_chan_resources; |
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dma->device_issue_pending = moxart_issue_pending; |
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dma->device_tx_status = moxart_tx_status; |
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dma->device_config = moxart_slave_config; |
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dma->device_terminate_all = moxart_terminate_all; |
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dma->dev = dev; |
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INIT_LIST_HEAD(&dma->channels); |
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} |
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static irqreturn_t moxart_dma_interrupt(int irq, void *devid) |
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{ |
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struct moxart_dmadev *mc = devid; |
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struct moxart_chan *ch = &mc->slave_chans[0]; |
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unsigned int i; |
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u32 ctrl; |
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dev_dbg(chan2dev(&ch->vc.chan), "%s\n", __func__); |
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for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) { |
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if (!ch->allocated) |
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continue; |
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ctrl = readl(ch->base + REG_OFF_CTRL); |
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dev_dbg(chan2dev(&ch->vc.chan), "%s: ch=%p ch->base=%p ctrl=%x\n", |
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__func__, ch, ch->base, ctrl); |
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|
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if (ctrl & APB_DMA_FIN_INT_STS) { |
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ctrl &= ~APB_DMA_FIN_INT_STS; |
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if (ch->desc) { |
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spin_lock(&ch->vc.lock); |
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if (++ch->sgidx < ch->desc->sglen) { |
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moxart_dma_start_sg(ch, ch->sgidx); |
|
} else { |
|
vchan_cookie_complete(&ch->desc->vd); |
|
moxart_dma_start_desc(&ch->vc.chan); |
|
} |
|
spin_unlock(&ch->vc.lock); |
|
} |
|
} |
|
|
|
if (ctrl & APB_DMA_ERR_INT_STS) { |
|
ctrl &= ~APB_DMA_ERR_INT_STS; |
|
ch->error = 1; |
|
} |
|
|
|
writel(ctrl, ch->base + REG_OFF_CTRL); |
|
} |
|
|
|
return IRQ_HANDLED; |
|
} |
|
|
|
static int moxart_probe(struct platform_device *pdev) |
|
{ |
|
struct device *dev = &pdev->dev; |
|
struct device_node *node = dev->of_node; |
|
struct resource *res; |
|
void __iomem *dma_base_addr; |
|
int ret, i; |
|
unsigned int irq; |
|
struct moxart_chan *ch; |
|
struct moxart_dmadev *mdc; |
|
|
|
mdc = devm_kzalloc(dev, sizeof(*mdc), GFP_KERNEL); |
|
if (!mdc) |
|
return -ENOMEM; |
|
|
|
irq = irq_of_parse_and_map(node, 0); |
|
if (!irq) { |
|
dev_err(dev, "no IRQ resource\n"); |
|
return -EINVAL; |
|
} |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
dma_base_addr = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(dma_base_addr)) |
|
return PTR_ERR(dma_base_addr); |
|
|
|
dma_cap_zero(mdc->dma_slave.cap_mask); |
|
dma_cap_set(DMA_SLAVE, mdc->dma_slave.cap_mask); |
|
dma_cap_set(DMA_PRIVATE, mdc->dma_slave.cap_mask); |
|
|
|
moxart_dma_init(&mdc->dma_slave, dev); |
|
|
|
ch = &mdc->slave_chans[0]; |
|
for (i = 0; i < APB_DMA_MAX_CHANNEL; i++, ch++) { |
|
ch->ch_num = i; |
|
ch->base = dma_base_addr + i * REG_OFF_CHAN_SIZE; |
|
ch->allocated = 0; |
|
|
|
ch->vc.desc_free = moxart_dma_desc_free; |
|
vchan_init(&ch->vc, &mdc->dma_slave); |
|
|
|
dev_dbg(dev, "%s: chs[%d]: ch->ch_num=%u ch->base=%p\n", |
|
__func__, i, ch->ch_num, ch->base); |
|
} |
|
|
|
platform_set_drvdata(pdev, mdc); |
|
|
|
ret = devm_request_irq(dev, irq, moxart_dma_interrupt, 0, |
|
"moxart-dma-engine", mdc); |
|
if (ret) { |
|
dev_err(dev, "devm_request_irq failed\n"); |
|
return ret; |
|
} |
|
mdc->irq = irq; |
|
|
|
ret = dma_async_device_register(&mdc->dma_slave); |
|
if (ret) { |
|
dev_err(dev, "dma_async_device_register failed\n"); |
|
return ret; |
|
} |
|
|
|
ret = of_dma_controller_register(node, moxart_of_xlate, mdc); |
|
if (ret) { |
|
dev_err(dev, "of_dma_controller_register failed\n"); |
|
dma_async_device_unregister(&mdc->dma_slave); |
|
return ret; |
|
} |
|
|
|
dev_dbg(dev, "%s: IRQ=%u\n", __func__, irq); |
|
|
|
return 0; |
|
} |
|
|
|
static int moxart_remove(struct platform_device *pdev) |
|
{ |
|
struct moxart_dmadev *m = platform_get_drvdata(pdev); |
|
|
|
devm_free_irq(&pdev->dev, m->irq, m); |
|
|
|
dma_async_device_unregister(&m->dma_slave); |
|
|
|
if (pdev->dev.of_node) |
|
of_dma_controller_free(pdev->dev.of_node); |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id moxart_dma_match[] = { |
|
{ .compatible = "moxa,moxart-dma" }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(of, moxart_dma_match); |
|
|
|
static struct platform_driver moxart_driver = { |
|
.probe = moxart_probe, |
|
.remove = moxart_remove, |
|
.driver = { |
|
.name = "moxart-dma-engine", |
|
.of_match_table = moxart_dma_match, |
|
}, |
|
}; |
|
|
|
static int moxart_init(void) |
|
{ |
|
return platform_driver_register(&moxart_driver); |
|
} |
|
subsys_initcall(moxart_init); |
|
|
|
static void __exit moxart_exit(void) |
|
{ |
|
platform_driver_unregister(&moxart_driver); |
|
} |
|
module_exit(moxart_exit); |
|
|
|
MODULE_AUTHOR("Jonas Jensen <[email protected]>"); |
|
MODULE_DESCRIPTION("MOXART DMA engine driver"); |
|
MODULE_LICENSE("GPL v2");
|
|
|