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1078 lines
28 KiB
1078 lines
28 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* Copyright (c) 2018-2019 HiSilicon Limited. */ |
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#include <linux/acpi.h> |
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#include <linux/aer.h> |
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#include <linux/bitops.h> |
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#include <linux/debugfs.h> |
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#include <linux/init.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/topology.h> |
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#include <linux/uacce.h> |
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#include "hpre.h" |
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#define HPRE_QUEUE_NUM_V2 1024 |
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#define HPRE_QM_ABNML_INT_MASK 0x100004 |
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#define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) |
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#define HPRE_COMM_CNT_CLR_CE 0x0 |
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#define HPRE_CTRL_CNT_CLR_CE 0x301000 |
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#define HPRE_FSM_MAX_CNT 0x301008 |
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#define HPRE_VFG_AXQOS 0x30100c |
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#define HPRE_VFG_AXCACHE 0x301010 |
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#define HPRE_RDCHN_INI_CFG 0x301014 |
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#define HPRE_AWUSR_FP_CFG 0x301018 |
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#define HPRE_BD_ENDIAN 0x301020 |
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#define HPRE_ECC_BYPASS 0x301024 |
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#define HPRE_RAS_WIDTH_CFG 0x301028 |
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#define HPRE_POISON_BYPASS 0x30102c |
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#define HPRE_BD_ARUSR_CFG 0x301030 |
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#define HPRE_BD_AWUSR_CFG 0x301034 |
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#define HPRE_TYPES_ENB 0x301038 |
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#define HPRE_RSA_ENB BIT(0) |
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#define HPRE_ECC_ENB BIT(1) |
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#define HPRE_DATA_RUSER_CFG 0x30103c |
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#define HPRE_DATA_WUSER_CFG 0x301040 |
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#define HPRE_INT_MASK 0x301400 |
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#define HPRE_INT_STATUS 0x301800 |
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#define HPRE_CORE_INT_ENABLE 0 |
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#define HPRE_CORE_INT_DISABLE 0x003fffff |
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#define HPRE_RDCHN_INI_ST 0x301a00 |
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#define HPRE_CLSTR_BASE 0x302000 |
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#define HPRE_CORE_EN_OFFSET 0x04 |
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#define HPRE_CORE_INI_CFG_OFFSET 0x20 |
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#define HPRE_CORE_INI_STATUS_OFFSET 0x80 |
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#define HPRE_CORE_HTBT_WARN_OFFSET 0x8c |
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#define HPRE_CORE_IS_SCHD_OFFSET 0x90 |
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#define HPRE_RAS_CE_ENB 0x301410 |
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#define HPRE_HAC_RAS_CE_ENABLE (BIT(0) | BIT(22) | BIT(23)) |
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#define HPRE_RAS_NFE_ENB 0x301414 |
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#define HPRE_HAC_RAS_NFE_ENABLE 0x3ffffe |
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#define HPRE_RAS_FE_ENB 0x301418 |
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#define HPRE_HAC_RAS_FE_ENABLE 0 |
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#define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) |
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#define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) |
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#define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) |
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#define HPRE_HAC_ECC1_CNT 0x301a04 |
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#define HPRE_HAC_ECC2_CNT 0x301a08 |
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#define HPRE_HAC_INT_STATUS 0x301800 |
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#define HPRE_HAC_SOURCE_INT 0x301600 |
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#define HPRE_CLSTR_ADDR_INTRVL 0x1000 |
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#define HPRE_CLUSTER_INQURY 0x100 |
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#define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 |
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#define HPRE_TIMEOUT_ABNML_BIT 6 |
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#define HPRE_PASID_EN_BIT 9 |
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#define HPRE_REG_RD_INTVRL_US 10 |
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#define HPRE_REG_RD_TMOUT_US 1000 |
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#define HPRE_DBGFS_VAL_MAX_LEN 20 |
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#define HPRE_PCI_DEVICE_ID 0xa258 |
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#define HPRE_PCI_VF_DEVICE_ID 0xa259 |
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#define HPRE_ADDR(qm, offset) ((qm)->io_base + (offset)) |
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#define HPRE_QM_USR_CFG_MASK 0xfffffffe |
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#define HPRE_QM_AXI_CFG_MASK 0xffff |
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#define HPRE_QM_VFG_AX_MASK 0xff |
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#define HPRE_BD_USR_MASK 0x3 |
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#define HPRE_CLUSTER_CORE_MASK_V2 0xf |
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#define HPRE_CLUSTER_CORE_MASK_V3 0xff |
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#define HPRE_AM_OOO_SHUTDOWN_ENB 0x301044 |
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#define HPRE_AM_OOO_SHUTDOWN_ENABLE BIT(0) |
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#define HPRE_WR_MSI_PORT BIT(2) |
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#define HPRE_CORE_ECC_2BIT_ERR BIT(1) |
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#define HPRE_OOO_ECC_2BIT_ERR BIT(5) |
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#define HPRE_QM_BME_FLR BIT(7) |
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#define HPRE_QM_PM_FLR BIT(11) |
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#define HPRE_QM_SRIOV_FLR BIT(12) |
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#define HPRE_CLUSTERS_NUM(qm) \ |
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(((qm)->ver >= QM_HW_V3) ? HPRE_CLUSTERS_NUM_V3 : HPRE_CLUSTERS_NUM_V2) |
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#define HPRE_CLUSTER_CORE_MASK(qm) \ |
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(((qm)->ver >= QM_HW_V3) ? HPRE_CLUSTER_CORE_MASK_V3 :\ |
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HPRE_CLUSTER_CORE_MASK_V2) |
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#define HPRE_VIA_MSI_DSM 1 |
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#define HPRE_SQE_MASK_OFFSET 8 |
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#define HPRE_SQE_MASK_LEN 24 |
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static const char hpre_name[] = "hisi_hpre"; |
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static struct dentry *hpre_debugfs_root; |
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static const struct pci_device_id hpre_dev_ids[] = { |
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{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_DEVICE_ID) }, |
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{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_VF_DEVICE_ID) }, |
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{ 0, } |
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}; |
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MODULE_DEVICE_TABLE(pci, hpre_dev_ids); |
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struct hpre_hw_error { |
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u32 int_msk; |
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const char *msg; |
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}; |
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static struct hisi_qm_list hpre_devices = { |
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.register_to_crypto = hpre_algs_register, |
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.unregister_from_crypto = hpre_algs_unregister, |
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}; |
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static const char * const hpre_debug_file_name[] = { |
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[HPRE_CURRENT_QM] = "current_qm", |
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[HPRE_CLEAR_ENABLE] = "rdclr_en", |
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[HPRE_CLUSTER_CTRL] = "cluster_ctrl", |
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}; |
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static const struct hpre_hw_error hpre_hw_errors[] = { |
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{ .int_msk = BIT(0), .msg = "core_ecc_1bit_err_int_set" }, |
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{ .int_msk = BIT(1), .msg = "core_ecc_2bit_err_int_set" }, |
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{ .int_msk = BIT(2), .msg = "dat_wb_poison_int_set" }, |
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{ .int_msk = BIT(3), .msg = "dat_rd_poison_int_set" }, |
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{ .int_msk = BIT(4), .msg = "bd_rd_poison_int_set" }, |
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{ .int_msk = BIT(5), .msg = "ooo_ecc_2bit_err_int_set" }, |
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{ .int_msk = BIT(6), .msg = "cluster1_shb_timeout_int_set" }, |
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{ .int_msk = BIT(7), .msg = "cluster2_shb_timeout_int_set" }, |
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{ .int_msk = BIT(8), .msg = "cluster3_shb_timeout_int_set" }, |
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{ .int_msk = BIT(9), .msg = "cluster4_shb_timeout_int_set" }, |
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{ .int_msk = GENMASK(15, 10), .msg = "ooo_rdrsp_err_int_set" }, |
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{ .int_msk = GENMASK(21, 16), .msg = "ooo_wrrsp_err_int_set" }, |
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{ .int_msk = BIT(22), .msg = "pt_rng_timeout_int_set"}, |
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{ .int_msk = BIT(23), .msg = "sva_fsm_timeout_int_set"}, |
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{ |
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/* sentinel */ |
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} |
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}; |
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static const u64 hpre_cluster_offsets[] = { |
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[HPRE_CLUSTER0] = |
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HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, |
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[HPRE_CLUSTER1] = |
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HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, |
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[HPRE_CLUSTER2] = |
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HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, |
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[HPRE_CLUSTER3] = |
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HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, |
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}; |
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static const struct debugfs_reg32 hpre_cluster_dfx_regs[] = { |
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{"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, |
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{"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, |
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{"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, |
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{"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, |
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{"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, |
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}; |
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static const struct debugfs_reg32 hpre_com_dfx_regs[] = { |
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{"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, |
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{"AXQOS ", HPRE_VFG_AXQOS}, |
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{"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, |
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{"QM_ARUSR_MCFG1 ", QM_ARUSER_M_CFG_1}, |
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{"QM_AWUSR_MCFG1 ", QM_AWUSER_M_CFG_1}, |
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{"BD_ENDIAN ", HPRE_BD_ENDIAN}, |
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{"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, |
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{"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, |
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{"POISON_BYPASS ", HPRE_POISON_BYPASS}, |
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{"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, |
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{"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, |
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{"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, |
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{"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, |
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{"INT_STATUS ", HPRE_INT_STATUS}, |
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}; |
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static const char *hpre_dfx_files[HPRE_DFX_FILE_NUM] = { |
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"send_cnt", |
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"recv_cnt", |
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"send_fail_cnt", |
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"send_busy_cnt", |
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"over_thrhld_cnt", |
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"overtime_thrhld", |
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"invalid_req_cnt" |
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}; |
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static const struct kernel_param_ops hpre_uacce_mode_ops = { |
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.set = uacce_mode_set, |
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.get = param_get_int, |
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}; |
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/* |
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* uacce_mode = 0 means hpre only register to crypto, |
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* uacce_mode = 1 means hpre both register to crypto and uacce. |
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*/ |
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static u32 uacce_mode = UACCE_MODE_NOUACCE; |
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module_param_cb(uacce_mode, &hpre_uacce_mode_ops, &uacce_mode, 0444); |
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MODULE_PARM_DESC(uacce_mode, UACCE_MODE_DESC); |
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static int pf_q_num_set(const char *val, const struct kernel_param *kp) |
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{ |
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return q_num_set(val, kp, HPRE_PCI_DEVICE_ID); |
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} |
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static const struct kernel_param_ops hpre_pf_q_num_ops = { |
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.set = pf_q_num_set, |
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.get = param_get_int, |
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}; |
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static u32 pf_q_num = HPRE_PF_DEF_Q_NUM; |
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module_param_cb(pf_q_num, &hpre_pf_q_num_ops, &pf_q_num, 0444); |
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MODULE_PARM_DESC(pf_q_num, "Number of queues in PF of CS(2-1024)"); |
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static const struct kernel_param_ops vfs_num_ops = { |
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.set = vfs_num_set, |
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.get = param_get_int, |
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}; |
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static u32 vfs_num; |
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module_param_cb(vfs_num, &vfs_num_ops, &vfs_num, 0444); |
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MODULE_PARM_DESC(vfs_num, "Number of VFs to enable(1-63), 0(default)"); |
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struct hisi_qp *hpre_create_qp(void) |
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{ |
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int node = cpu_to_node(smp_processor_id()); |
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struct hisi_qp *qp = NULL; |
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int ret; |
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ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, 0, node, &qp); |
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if (!ret) |
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return qp; |
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return NULL; |
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} |
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static void hpre_pasid_enable(struct hisi_qm *qm) |
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{ |
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u32 val; |
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val = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); |
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val |= BIT(HPRE_PASID_EN_BIT); |
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writel_relaxed(val, qm->io_base + HPRE_DATA_RUSER_CFG); |
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val = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); |
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val |= BIT(HPRE_PASID_EN_BIT); |
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writel_relaxed(val, qm->io_base + HPRE_DATA_WUSER_CFG); |
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} |
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static void hpre_pasid_disable(struct hisi_qm *qm) |
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{ |
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u32 val; |
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val = readl_relaxed(qm->io_base + HPRE_DATA_RUSER_CFG); |
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val &= ~BIT(HPRE_PASID_EN_BIT); |
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writel_relaxed(val, qm->io_base + HPRE_DATA_RUSER_CFG); |
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val = readl_relaxed(qm->io_base + HPRE_DATA_WUSER_CFG); |
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val &= ~BIT(HPRE_PASID_EN_BIT); |
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writel_relaxed(val, qm->io_base + HPRE_DATA_WUSER_CFG); |
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} |
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static int hpre_cfg_by_dsm(struct hisi_qm *qm) |
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{ |
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struct device *dev = &qm->pdev->dev; |
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union acpi_object *obj; |
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guid_t guid; |
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if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { |
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dev_err(dev, "Hpre GUID failed\n"); |
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return -EINVAL; |
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} |
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/* Switch over to MSI handling due to non-standard PCI implementation */ |
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obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, |
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0, HPRE_VIA_MSI_DSM, NULL); |
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if (!obj) { |
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dev_err(dev, "ACPI handle failed!\n"); |
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return -EIO; |
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} |
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ACPI_FREE(obj); |
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return 0; |
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} |
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static int hpre_set_cluster(struct hisi_qm *qm) |
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{ |
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u32 cluster_core_mask = HPRE_CLUSTER_CORE_MASK(qm); |
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u8 clusters_num = HPRE_CLUSTERS_NUM(qm); |
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struct device *dev = &qm->pdev->dev; |
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unsigned long offset; |
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u32 val = 0; |
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int ret, i; |
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for (i = 0; i < clusters_num; i++) { |
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offset = i * HPRE_CLSTR_ADDR_INTRVL; |
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/* clusters initiating */ |
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writel(cluster_core_mask, |
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HPRE_ADDR(qm, offset + HPRE_CORE_ENB)); |
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writel(0x1, HPRE_ADDR(qm, offset + HPRE_CORE_INI_CFG)); |
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ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, offset + |
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HPRE_CORE_INI_STATUS), val, |
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((val & cluster_core_mask) == |
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cluster_core_mask), |
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HPRE_REG_RD_INTVRL_US, |
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HPRE_REG_RD_TMOUT_US); |
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if (ret) { |
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dev_err(dev, |
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"cluster %d int st status timeout!\n", i); |
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return -ETIMEDOUT; |
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} |
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} |
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return 0; |
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} |
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/* |
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* For Kunpeng 920, we shoul disable FLR triggered by hardware (BME/PM/SRIOV). |
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* Or it may stay in D3 state when we bind and unbind hpre quickly, |
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* as it does FLR triggered by hardware. |
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*/ |
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static void disable_flr_of_bme(struct hisi_qm *qm) |
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{ |
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u32 val; |
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val = readl(HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); |
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val &= ~(HPRE_QM_BME_FLR | HPRE_QM_SRIOV_FLR); |
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val |= HPRE_QM_PM_FLR; |
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writel(val, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); |
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writel(PEH_AXUSER_CFG_ENABLE, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG_ENABLE)); |
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} |
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static int hpre_set_user_domain_and_cache(struct hisi_qm *qm) |
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{ |
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struct device *dev = &qm->pdev->dev; |
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u32 val; |
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int ret; |
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writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_ARUSER_M_CFG_ENABLE)); |
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writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_AWUSER_M_CFG_ENABLE)); |
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writel_relaxed(HPRE_QM_AXI_CFG_MASK, HPRE_ADDR(qm, QM_AXI_M_CFG)); |
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/* HPRE need more time, we close this interrupt */ |
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val = readl_relaxed(HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK)); |
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val |= BIT(HPRE_TIMEOUT_ABNML_BIT); |
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writel_relaxed(val, HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK)); |
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if (qm->ver >= QM_HW_V3) |
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writel(HPRE_RSA_ENB | HPRE_ECC_ENB, |
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HPRE_ADDR(qm, HPRE_TYPES_ENB)); |
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else |
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writel(HPRE_RSA_ENB, HPRE_ADDR(qm, HPRE_TYPES_ENB)); |
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writel(HPRE_QM_VFG_AX_MASK, HPRE_ADDR(qm, HPRE_VFG_AXCACHE)); |
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writel(0x0, HPRE_ADDR(qm, HPRE_BD_ENDIAN)); |
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writel(0x0, HPRE_ADDR(qm, HPRE_INT_MASK)); |
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writel(0x0, HPRE_ADDR(qm, HPRE_POISON_BYPASS)); |
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writel(0x0, HPRE_ADDR(qm, HPRE_COMM_CNT_CLR_CE)); |
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writel(0x0, HPRE_ADDR(qm, HPRE_ECC_BYPASS)); |
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writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_ARUSR_CFG)); |
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writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_AWUSR_CFG)); |
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writel(0x1, HPRE_ADDR(qm, HPRE_RDCHN_INI_CFG)); |
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ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, HPRE_RDCHN_INI_ST), val, |
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val & BIT(0), |
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HPRE_REG_RD_INTVRL_US, |
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HPRE_REG_RD_TMOUT_US); |
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if (ret) { |
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dev_err(dev, "read rd channel timeout fail!\n"); |
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return -ETIMEDOUT; |
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} |
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ret = hpre_set_cluster(qm); |
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if (ret) |
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return -ETIMEDOUT; |
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/* This setting is only needed by Kunpeng 920. */ |
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if (qm->ver == QM_HW_V2) { |
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ret = hpre_cfg_by_dsm(qm); |
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if (ret) |
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dev_err(dev, "acpi_evaluate_dsm err.\n"); |
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disable_flr_of_bme(qm); |
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/* Enable data buffer pasid */ |
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if (qm->use_sva) |
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hpre_pasid_enable(qm); |
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} |
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return ret; |
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} |
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static void hpre_cnt_regs_clear(struct hisi_qm *qm) |
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{ |
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u8 clusters_num = HPRE_CLUSTERS_NUM(qm); |
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unsigned long offset; |
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int i; |
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/* clear current_qm */ |
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writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); |
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writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); |
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/* clear clusterX/cluster_ctrl */ |
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for (i = 0; i < clusters_num; i++) { |
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offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; |
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writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); |
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} |
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/* clear rdclr_en */ |
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writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); |
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hisi_qm_debug_regs_clear(qm); |
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} |
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static void hpre_hw_error_disable(struct hisi_qm *qm) |
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{ |
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u32 val; |
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/* disable hpre hw error interrupts */ |
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writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_INT_MASK); |
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/* disable HPRE block master OOO when m-bit error occur */ |
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val = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); |
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val &= ~HPRE_AM_OOO_SHUTDOWN_ENABLE; |
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writel(val, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); |
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} |
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static void hpre_hw_error_enable(struct hisi_qm *qm) |
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{ |
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u32 val; |
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|
|
/* clear HPRE hw error source if having */ |
|
writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_HAC_SOURCE_INT); |
|
|
|
/* enable hpre hw error interrupts */ |
|
writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); |
|
writel(HPRE_HAC_RAS_CE_ENABLE, qm->io_base + HPRE_RAS_CE_ENB); |
|
writel(HPRE_HAC_RAS_NFE_ENABLE, qm->io_base + HPRE_RAS_NFE_ENB); |
|
writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); |
|
|
|
/* enable HPRE block master OOO when m-bit error occur */ |
|
val = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); |
|
val |= HPRE_AM_OOO_SHUTDOWN_ENABLE; |
|
writel(val, qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); |
|
} |
|
|
|
static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) |
|
{ |
|
struct hpre *hpre = container_of(file->debug, struct hpre, debug); |
|
|
|
return &hpre->qm; |
|
} |
|
|
|
static u32 hpre_current_qm_read(struct hpre_debugfs_file *file) |
|
{ |
|
struct hisi_qm *qm = hpre_file_to_qm(file); |
|
|
|
return readl(qm->io_base + QM_DFX_MB_CNT_VF); |
|
} |
|
|
|
static int hpre_current_qm_write(struct hpre_debugfs_file *file, u32 val) |
|
{ |
|
struct hisi_qm *qm = hpre_file_to_qm(file); |
|
u32 num_vfs = qm->vfs_num; |
|
u32 vfq_num, tmp; |
|
|
|
if (val > num_vfs) |
|
return -EINVAL; |
|
|
|
/* According PF or VF Dev ID to calculation curr_qm_qp_num and store */ |
|
if (val == 0) { |
|
qm->debug.curr_qm_qp_num = qm->qp_num; |
|
} else { |
|
vfq_num = (qm->ctrl_qp_num - qm->qp_num) / num_vfs; |
|
if (val == num_vfs) { |
|
qm->debug.curr_qm_qp_num = |
|
qm->ctrl_qp_num - qm->qp_num - (num_vfs - 1) * vfq_num; |
|
} else { |
|
qm->debug.curr_qm_qp_num = vfq_num; |
|
} |
|
} |
|
|
|
writel(val, qm->io_base + QM_DFX_MB_CNT_VF); |
|
writel(val, qm->io_base + QM_DFX_DB_CNT_VF); |
|
|
|
tmp = val | |
|
(readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK); |
|
writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); |
|
|
|
tmp = val | |
|
(readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK); |
|
writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); |
|
|
|
return 0; |
|
} |
|
|
|
static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) |
|
{ |
|
struct hisi_qm *qm = hpre_file_to_qm(file); |
|
|
|
return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & |
|
HPRE_CTRL_CNT_CLR_CE_BIT; |
|
} |
|
|
|
static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) |
|
{ |
|
struct hisi_qm *qm = hpre_file_to_qm(file); |
|
u32 tmp; |
|
|
|
if (val != 1 && val != 0) |
|
return -EINVAL; |
|
|
|
tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & |
|
~HPRE_CTRL_CNT_CLR_CE_BIT) | val; |
|
writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); |
|
|
|
return 0; |
|
} |
|
|
|
static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) |
|
{ |
|
struct hisi_qm *qm = hpre_file_to_qm(file); |
|
int cluster_index = file->index - HPRE_CLUSTER_CTRL; |
|
unsigned long offset = HPRE_CLSTR_BASE + |
|
cluster_index * HPRE_CLSTR_ADDR_INTRVL; |
|
|
|
return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); |
|
} |
|
|
|
static int hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) |
|
{ |
|
struct hisi_qm *qm = hpre_file_to_qm(file); |
|
int cluster_index = file->index - HPRE_CLUSTER_CTRL; |
|
unsigned long offset = HPRE_CLSTR_BASE + cluster_index * |
|
HPRE_CLSTR_ADDR_INTRVL; |
|
|
|
writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); |
|
|
|
return 0; |
|
} |
|
|
|
static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, |
|
size_t count, loff_t *pos) |
|
{ |
|
struct hpre_debugfs_file *file = filp->private_data; |
|
char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; |
|
u32 val; |
|
int ret; |
|
|
|
spin_lock_irq(&file->lock); |
|
switch (file->type) { |
|
case HPRE_CURRENT_QM: |
|
val = hpre_current_qm_read(file); |
|
break; |
|
case HPRE_CLEAR_ENABLE: |
|
val = hpre_clear_enable_read(file); |
|
break; |
|
case HPRE_CLUSTER_CTRL: |
|
val = hpre_cluster_inqry_read(file); |
|
break; |
|
default: |
|
spin_unlock_irq(&file->lock); |
|
return -EINVAL; |
|
} |
|
spin_unlock_irq(&file->lock); |
|
ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); |
|
return simple_read_from_buffer(buf, count, pos, tbuf, ret); |
|
} |
|
|
|
static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, |
|
size_t count, loff_t *pos) |
|
{ |
|
struct hpre_debugfs_file *file = filp->private_data; |
|
char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; |
|
unsigned long val; |
|
int len, ret; |
|
|
|
if (*pos != 0) |
|
return 0; |
|
|
|
if (count >= HPRE_DBGFS_VAL_MAX_LEN) |
|
return -ENOSPC; |
|
|
|
len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, |
|
pos, buf, count); |
|
if (len < 0) |
|
return len; |
|
|
|
tbuf[len] = '\0'; |
|
if (kstrtoul(tbuf, 0, &val)) |
|
return -EFAULT; |
|
|
|
spin_lock_irq(&file->lock); |
|
switch (file->type) { |
|
case HPRE_CURRENT_QM: |
|
ret = hpre_current_qm_write(file, val); |
|
if (ret) |
|
goto err_input; |
|
break; |
|
case HPRE_CLEAR_ENABLE: |
|
ret = hpre_clear_enable_write(file, val); |
|
if (ret) |
|
goto err_input; |
|
break; |
|
case HPRE_CLUSTER_CTRL: |
|
ret = hpre_cluster_inqry_write(file, val); |
|
if (ret) |
|
goto err_input; |
|
break; |
|
default: |
|
ret = -EINVAL; |
|
goto err_input; |
|
} |
|
spin_unlock_irq(&file->lock); |
|
|
|
return count; |
|
|
|
err_input: |
|
spin_unlock_irq(&file->lock); |
|
return ret; |
|
} |
|
|
|
static const struct file_operations hpre_ctrl_debug_fops = { |
|
.owner = THIS_MODULE, |
|
.open = simple_open, |
|
.read = hpre_ctrl_debug_read, |
|
.write = hpre_ctrl_debug_write, |
|
}; |
|
|
|
static int hpre_debugfs_atomic64_get(void *data, u64 *val) |
|
{ |
|
struct hpre_dfx *dfx_item = data; |
|
|
|
*val = atomic64_read(&dfx_item->value); |
|
|
|
return 0; |
|
} |
|
|
|
static int hpre_debugfs_atomic64_set(void *data, u64 val) |
|
{ |
|
struct hpre_dfx *dfx_item = data; |
|
struct hpre_dfx *hpre_dfx = NULL; |
|
|
|
if (dfx_item->type == HPRE_OVERTIME_THRHLD) { |
|
hpre_dfx = dfx_item - HPRE_OVERTIME_THRHLD; |
|
atomic64_set(&hpre_dfx[HPRE_OVER_THRHLD_CNT].value, 0); |
|
} else if (val) { |
|
return -EINVAL; |
|
} |
|
|
|
atomic64_set(&dfx_item->value, val); |
|
|
|
return 0; |
|
} |
|
|
|
DEFINE_DEBUGFS_ATTRIBUTE(hpre_atomic64_ops, hpre_debugfs_atomic64_get, |
|
hpre_debugfs_atomic64_set, "%llu\n"); |
|
|
|
static int hpre_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir, |
|
enum hpre_ctrl_dbgfs_file type, int indx) |
|
{ |
|
struct hpre *hpre = container_of(qm, struct hpre, qm); |
|
struct hpre_debug *dbg = &hpre->debug; |
|
struct dentry *file_dir; |
|
|
|
if (dir) |
|
file_dir = dir; |
|
else |
|
file_dir = qm->debug.debug_root; |
|
|
|
if (type >= HPRE_DEBUG_FILE_NUM) |
|
return -EINVAL; |
|
|
|
spin_lock_init(&dbg->files[indx].lock); |
|
dbg->files[indx].debug = dbg; |
|
dbg->files[indx].type = type; |
|
dbg->files[indx].index = indx; |
|
debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, |
|
dbg->files + indx, &hpre_ctrl_debug_fops); |
|
|
|
return 0; |
|
} |
|
|
|
static int hpre_pf_comm_regs_debugfs_init(struct hisi_qm *qm) |
|
{ |
|
struct device *dev = &qm->pdev->dev; |
|
struct debugfs_regset32 *regset; |
|
|
|
regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); |
|
if (!regset) |
|
return -ENOMEM; |
|
|
|
regset->regs = hpre_com_dfx_regs; |
|
regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); |
|
regset->base = qm->io_base; |
|
|
|
debugfs_create_regset32("regs", 0444, qm->debug.debug_root, regset); |
|
return 0; |
|
} |
|
|
|
static int hpre_cluster_debugfs_init(struct hisi_qm *qm) |
|
{ |
|
u8 clusters_num = HPRE_CLUSTERS_NUM(qm); |
|
struct device *dev = &qm->pdev->dev; |
|
char buf[HPRE_DBGFS_VAL_MAX_LEN]; |
|
struct debugfs_regset32 *regset; |
|
struct dentry *tmp_d; |
|
int i, ret; |
|
|
|
for (i = 0; i < clusters_num; i++) { |
|
ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); |
|
if (ret < 0) |
|
return -EINVAL; |
|
tmp_d = debugfs_create_dir(buf, qm->debug.debug_root); |
|
|
|
regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); |
|
if (!regset) |
|
return -ENOMEM; |
|
|
|
regset->regs = hpre_cluster_dfx_regs; |
|
regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); |
|
regset->base = qm->io_base + hpre_cluster_offsets[i]; |
|
|
|
debugfs_create_regset32("regs", 0444, tmp_d, regset); |
|
ret = hpre_create_debugfs_file(qm, tmp_d, HPRE_CLUSTER_CTRL, |
|
i + HPRE_CLUSTER_CTRL); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int hpre_ctrl_debug_init(struct hisi_qm *qm) |
|
{ |
|
int ret; |
|
|
|
ret = hpre_create_debugfs_file(qm, NULL, HPRE_CURRENT_QM, |
|
HPRE_CURRENT_QM); |
|
if (ret) |
|
return ret; |
|
|
|
ret = hpre_create_debugfs_file(qm, NULL, HPRE_CLEAR_ENABLE, |
|
HPRE_CLEAR_ENABLE); |
|
if (ret) |
|
return ret; |
|
|
|
ret = hpre_pf_comm_regs_debugfs_init(qm); |
|
if (ret) |
|
return ret; |
|
|
|
return hpre_cluster_debugfs_init(qm); |
|
} |
|
|
|
static void hpre_dfx_debug_init(struct hisi_qm *qm) |
|
{ |
|
struct hpre *hpre = container_of(qm, struct hpre, qm); |
|
struct hpre_dfx *dfx = hpre->debug.dfx; |
|
struct dentry *parent; |
|
int i; |
|
|
|
parent = debugfs_create_dir("hpre_dfx", qm->debug.debug_root); |
|
for (i = 0; i < HPRE_DFX_FILE_NUM; i++) { |
|
dfx[i].type = i; |
|
debugfs_create_file(hpre_dfx_files[i], 0644, parent, &dfx[i], |
|
&hpre_atomic64_ops); |
|
} |
|
} |
|
|
|
static int hpre_debugfs_init(struct hisi_qm *qm) |
|
{ |
|
struct device *dev = &qm->pdev->dev; |
|
int ret; |
|
|
|
qm->debug.debug_root = debugfs_create_dir(dev_name(dev), |
|
hpre_debugfs_root); |
|
|
|
qm->debug.sqe_mask_offset = HPRE_SQE_MASK_OFFSET; |
|
qm->debug.sqe_mask_len = HPRE_SQE_MASK_LEN; |
|
hisi_qm_debug_init(qm); |
|
|
|
if (qm->pdev->device == HPRE_PCI_DEVICE_ID) { |
|
ret = hpre_ctrl_debug_init(qm); |
|
if (ret) |
|
goto failed_to_create; |
|
} |
|
|
|
hpre_dfx_debug_init(qm); |
|
|
|
return 0; |
|
|
|
failed_to_create: |
|
debugfs_remove_recursive(qm->debug.debug_root); |
|
return ret; |
|
} |
|
|
|
static void hpre_debugfs_exit(struct hisi_qm *qm) |
|
{ |
|
debugfs_remove_recursive(qm->debug.debug_root); |
|
} |
|
|
|
static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) |
|
{ |
|
if (pdev->revision == QM_HW_V1) { |
|
pci_warn(pdev, "HPRE version 1 is not supported!\n"); |
|
return -EINVAL; |
|
} |
|
|
|
if (pdev->revision >= QM_HW_V3) |
|
qm->algs = "rsa\ndh\necdh\nx25519\nx448\necdsa\nsm2\n"; |
|
else |
|
qm->algs = "rsa\ndh\n"; |
|
qm->mode = uacce_mode; |
|
qm->pdev = pdev; |
|
qm->ver = pdev->revision; |
|
qm->sqe_size = HPRE_SQE_SIZE; |
|
qm->dev_name = hpre_name; |
|
|
|
qm->fun_type = (pdev->device == HPRE_PCI_DEVICE_ID) ? |
|
QM_HW_PF : QM_HW_VF; |
|
if (qm->fun_type == QM_HW_PF) { |
|
qm->qp_base = HPRE_PF_DEF_Q_BASE; |
|
qm->qp_num = pf_q_num; |
|
qm->debug.curr_qm_qp_num = pf_q_num; |
|
qm->qm_list = &hpre_devices; |
|
} |
|
|
|
return hisi_qm_init(qm); |
|
} |
|
|
|
static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) |
|
{ |
|
const struct hpre_hw_error *err = hpre_hw_errors; |
|
struct device *dev = &qm->pdev->dev; |
|
|
|
while (err->msg) { |
|
if (err->int_msk & err_sts) |
|
dev_warn(dev, "%s [error status=0x%x] found\n", |
|
err->msg, err->int_msk); |
|
err++; |
|
} |
|
} |
|
|
|
static u32 hpre_get_hw_err_status(struct hisi_qm *qm) |
|
{ |
|
return readl(qm->io_base + HPRE_HAC_INT_STATUS); |
|
} |
|
|
|
static void hpre_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) |
|
{ |
|
writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); |
|
} |
|
|
|
static void hpre_open_axi_master_ooo(struct hisi_qm *qm) |
|
{ |
|
u32 value; |
|
|
|
value = readl(qm->io_base + HPRE_AM_OOO_SHUTDOWN_ENB); |
|
writel(value & ~HPRE_AM_OOO_SHUTDOWN_ENABLE, |
|
HPRE_ADDR(qm, HPRE_AM_OOO_SHUTDOWN_ENB)); |
|
writel(value | HPRE_AM_OOO_SHUTDOWN_ENABLE, |
|
HPRE_ADDR(qm, HPRE_AM_OOO_SHUTDOWN_ENB)); |
|
} |
|
|
|
static const struct hisi_qm_err_ini hpre_err_ini = { |
|
.hw_init = hpre_set_user_domain_and_cache, |
|
.hw_err_enable = hpre_hw_error_enable, |
|
.hw_err_disable = hpre_hw_error_disable, |
|
.get_dev_hw_err_status = hpre_get_hw_err_status, |
|
.clear_dev_hw_err_status = hpre_clear_hw_err_status, |
|
.log_dev_hw_err = hpre_log_hw_error, |
|
.open_axi_master_ooo = hpre_open_axi_master_ooo, |
|
.err_info = { |
|
.ce = QM_BASE_CE, |
|
.nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT, |
|
.fe = 0, |
|
.ecc_2bits_mask = HPRE_CORE_ECC_2BIT_ERR | |
|
HPRE_OOO_ECC_2BIT_ERR, |
|
.dev_ce_mask = HPRE_HAC_RAS_CE_ENABLE, |
|
.msi_wr_port = HPRE_WR_MSI_PORT, |
|
.acpi_rst = "HRST", |
|
} |
|
}; |
|
|
|
static int hpre_pf_probe_init(struct hpre *hpre) |
|
{ |
|
struct hisi_qm *qm = &hpre->qm; |
|
int ret; |
|
|
|
qm->ctrl_qp_num = HPRE_QUEUE_NUM_V2; |
|
|
|
ret = hpre_set_user_domain_and_cache(qm); |
|
if (ret) |
|
return ret; |
|
|
|
qm->err_ini = &hpre_err_ini; |
|
hisi_qm_dev_err_init(qm); |
|
|
|
return 0; |
|
} |
|
|
|
static int hpre_probe_init(struct hpre *hpre) |
|
{ |
|
struct hisi_qm *qm = &hpre->qm; |
|
int ret; |
|
|
|
if (qm->fun_type == QM_HW_PF) { |
|
ret = hpre_pf_probe_init(hpre); |
|
if (ret) |
|
return ret; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
|
{ |
|
struct hisi_qm *qm; |
|
struct hpre *hpre; |
|
int ret; |
|
|
|
hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); |
|
if (!hpre) |
|
return -ENOMEM; |
|
|
|
qm = &hpre->qm; |
|
ret = hpre_qm_init(qm, pdev); |
|
if (ret) { |
|
pci_err(pdev, "Failed to init HPRE QM (%d)!\n", ret); |
|
return ret; |
|
} |
|
|
|
ret = hpre_probe_init(hpre); |
|
if (ret) { |
|
pci_err(pdev, "Failed to probe (%d)!\n", ret); |
|
goto err_with_qm_init; |
|
} |
|
|
|
ret = hisi_qm_start(qm); |
|
if (ret) |
|
goto err_with_err_init; |
|
|
|
ret = hpre_debugfs_init(qm); |
|
if (ret) |
|
dev_warn(&pdev->dev, "init debugfs fail!\n"); |
|
|
|
ret = hisi_qm_alg_register(qm, &hpre_devices); |
|
if (ret < 0) { |
|
pci_err(pdev, "fail to register algs to crypto!\n"); |
|
goto err_with_qm_start; |
|
} |
|
|
|
if (qm->uacce) { |
|
ret = uacce_register(qm->uacce); |
|
if (ret) { |
|
pci_err(pdev, "failed to register uacce (%d)!\n", ret); |
|
goto err_with_alg_register; |
|
} |
|
} |
|
|
|
if (qm->fun_type == QM_HW_PF && vfs_num) { |
|
ret = hisi_qm_sriov_enable(pdev, vfs_num); |
|
if (ret < 0) |
|
goto err_with_alg_register; |
|
} |
|
|
|
return 0; |
|
|
|
err_with_alg_register: |
|
hisi_qm_alg_unregister(qm, &hpre_devices); |
|
|
|
err_with_qm_start: |
|
hpre_debugfs_exit(qm); |
|
hisi_qm_stop(qm, QM_NORMAL); |
|
|
|
err_with_err_init: |
|
hisi_qm_dev_err_uninit(qm); |
|
|
|
err_with_qm_init: |
|
hisi_qm_uninit(qm); |
|
|
|
return ret; |
|
} |
|
|
|
static void hpre_remove(struct pci_dev *pdev) |
|
{ |
|
struct hisi_qm *qm = pci_get_drvdata(pdev); |
|
int ret; |
|
|
|
hisi_qm_wait_task_finish(qm, &hpre_devices); |
|
hisi_qm_alg_unregister(qm, &hpre_devices); |
|
if (qm->fun_type == QM_HW_PF && qm->vfs_num) { |
|
ret = hisi_qm_sriov_disable(pdev, true); |
|
if (ret) { |
|
pci_err(pdev, "Disable SRIOV fail!\n"); |
|
return; |
|
} |
|
} |
|
|
|
hpre_debugfs_exit(qm); |
|
hisi_qm_stop(qm, QM_NORMAL); |
|
|
|
if (qm->fun_type == QM_HW_PF) { |
|
if (qm->use_sva && qm->ver == QM_HW_V2) |
|
hpre_pasid_disable(qm); |
|
hpre_cnt_regs_clear(qm); |
|
qm->debug.curr_qm_qp_num = 0; |
|
hisi_qm_dev_err_uninit(qm); |
|
} |
|
|
|
hisi_qm_uninit(qm); |
|
} |
|
|
|
|
|
static const struct pci_error_handlers hpre_err_handler = { |
|
.error_detected = hisi_qm_dev_err_detected, |
|
.slot_reset = hisi_qm_dev_slot_reset, |
|
.reset_prepare = hisi_qm_reset_prepare, |
|
.reset_done = hisi_qm_reset_done, |
|
}; |
|
|
|
static struct pci_driver hpre_pci_driver = { |
|
.name = hpre_name, |
|
.id_table = hpre_dev_ids, |
|
.probe = hpre_probe, |
|
.remove = hpre_remove, |
|
.sriov_configure = IS_ENABLED(CONFIG_PCI_IOV) ? |
|
hisi_qm_sriov_configure : NULL, |
|
.err_handler = &hpre_err_handler, |
|
.shutdown = hisi_qm_dev_shutdown, |
|
}; |
|
|
|
static void hpre_register_debugfs(void) |
|
{ |
|
if (!debugfs_initialized()) |
|
return; |
|
|
|
hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); |
|
} |
|
|
|
static void hpre_unregister_debugfs(void) |
|
{ |
|
debugfs_remove_recursive(hpre_debugfs_root); |
|
} |
|
|
|
static int __init hpre_init(void) |
|
{ |
|
int ret; |
|
|
|
hisi_qm_init_list(&hpre_devices); |
|
hpre_register_debugfs(); |
|
|
|
ret = pci_register_driver(&hpre_pci_driver); |
|
if (ret) { |
|
hpre_unregister_debugfs(); |
|
pr_err("hpre: can't register hisi hpre driver.\n"); |
|
} |
|
|
|
return ret; |
|
} |
|
|
|
static void __exit hpre_exit(void) |
|
{ |
|
pci_unregister_driver(&hpre_pci_driver); |
|
hpre_unregister_debugfs(); |
|
} |
|
|
|
module_init(hpre_init); |
|
module_exit(hpre_exit); |
|
|
|
MODULE_LICENSE("GPL v2"); |
|
MODULE_AUTHOR("Zaibo Xu <[email protected]>"); |
|
MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator");
|
|
|