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366 lines
9.6 KiB
366 lines
9.6 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* TI DaVinci clocksource driver |
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* |
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* Copyright (C) 2019 Texas Instruments |
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* Author: Bartosz Golaszewski <[email protected]> |
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* (with tiny parts adopted from code by Kevin Hilman <[email protected]>) |
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*/ |
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#define pr_fmt(fmt) "%s: " fmt, __func__ |
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#include <linux/clk.h> |
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#include <linux/clockchips.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/sched_clock.h> |
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#include <clocksource/timer-davinci.h> |
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#define DAVINCI_TIMER_REG_TIM12 0x10 |
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#define DAVINCI_TIMER_REG_TIM34 0x14 |
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#define DAVINCI_TIMER_REG_PRD12 0x18 |
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#define DAVINCI_TIMER_REG_PRD34 0x1c |
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#define DAVINCI_TIMER_REG_TCR 0x20 |
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#define DAVINCI_TIMER_REG_TGCR 0x24 |
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#define DAVINCI_TIMER_TIMMODE_MASK GENMASK(3, 2) |
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#define DAVINCI_TIMER_RESET_MASK GENMASK(1, 0) |
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#define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED BIT(2) |
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#define DAVINCI_TIMER_UNRESET GENMASK(1, 0) |
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#define DAVINCI_TIMER_ENAMODE_MASK GENMASK(1, 0) |
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#define DAVINCI_TIMER_ENAMODE_DISABLED 0x00 |
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#define DAVINCI_TIMER_ENAMODE_ONESHOT BIT(0) |
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#define DAVINCI_TIMER_ENAMODE_PERIODIC BIT(1) |
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#define DAVINCI_TIMER_ENAMODE_SHIFT_TIM12 6 |
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#define DAVINCI_TIMER_ENAMODE_SHIFT_TIM34 22 |
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#define DAVINCI_TIMER_MIN_DELTA 0x01 |
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#define DAVINCI_TIMER_MAX_DELTA 0xfffffffe |
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#define DAVINCI_TIMER_CLKSRC_BITS 32 |
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#define DAVINCI_TIMER_TGCR_DEFAULT \ |
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(DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET) |
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struct davinci_clockevent { |
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struct clock_event_device dev; |
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void __iomem *base; |
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unsigned int cmp_off; |
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}; |
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/* |
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* This must be globally accessible by davinci_timer_read_sched_clock(), so |
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* let's keep it here. |
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*/ |
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static struct { |
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struct clocksource dev; |
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void __iomem *base; |
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unsigned int tim_off; |
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} davinci_clocksource; |
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static struct davinci_clockevent * |
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to_davinci_clockevent(struct clock_event_device *clockevent) |
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{ |
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return container_of(clockevent, struct davinci_clockevent, dev); |
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} |
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static unsigned int |
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davinci_clockevent_read(struct davinci_clockevent *clockevent, |
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unsigned int reg) |
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{ |
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return readl_relaxed(clockevent->base + reg); |
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} |
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static void davinci_clockevent_write(struct davinci_clockevent *clockevent, |
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unsigned int reg, unsigned int val) |
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{ |
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writel_relaxed(val, clockevent->base + reg); |
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} |
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static void davinci_tim12_shutdown(void __iomem *base) |
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{ |
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unsigned int tcr; |
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tcr = DAVINCI_TIMER_ENAMODE_DISABLED << |
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DAVINCI_TIMER_ENAMODE_SHIFT_TIM12; |
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/* |
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* This function is only ever called if we're using both timer |
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* halves. In this case TIM34 runs in periodic mode and we must |
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* not modify it. |
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*/ |
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tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC << |
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DAVINCI_TIMER_ENAMODE_SHIFT_TIM34; |
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writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); |
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} |
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static void davinci_tim12_set_oneshot(void __iomem *base) |
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{ |
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unsigned int tcr; |
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tcr = DAVINCI_TIMER_ENAMODE_ONESHOT << |
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DAVINCI_TIMER_ENAMODE_SHIFT_TIM12; |
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/* Same as above. */ |
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tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC << |
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DAVINCI_TIMER_ENAMODE_SHIFT_TIM34; |
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writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); |
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} |
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static int davinci_clockevent_shutdown(struct clock_event_device *dev) |
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{ |
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struct davinci_clockevent *clockevent; |
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clockevent = to_davinci_clockevent(dev); |
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davinci_tim12_shutdown(clockevent->base); |
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return 0; |
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} |
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static int davinci_clockevent_set_oneshot(struct clock_event_device *dev) |
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{ |
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struct davinci_clockevent *clockevent = to_davinci_clockevent(dev); |
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davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0); |
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davinci_tim12_set_oneshot(clockevent->base); |
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return 0; |
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} |
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static int |
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davinci_clockevent_set_next_event_std(unsigned long cycles, |
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struct clock_event_device *dev) |
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{ |
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struct davinci_clockevent *clockevent = to_davinci_clockevent(dev); |
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davinci_clockevent_shutdown(dev); |
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davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0); |
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davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_PRD12, cycles); |
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davinci_clockevent_set_oneshot(dev); |
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return 0; |
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} |
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static int |
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davinci_clockevent_set_next_event_cmp(unsigned long cycles, |
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struct clock_event_device *dev) |
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{ |
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struct davinci_clockevent *clockevent = to_davinci_clockevent(dev); |
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unsigned int curr_time; |
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curr_time = davinci_clockevent_read(clockevent, |
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DAVINCI_TIMER_REG_TIM12); |
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davinci_clockevent_write(clockevent, |
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clockevent->cmp_off, curr_time + cycles); |
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return 0; |
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} |
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static irqreturn_t davinci_timer_irq_timer(int irq, void *data) |
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{ |
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struct davinci_clockevent *clockevent = data; |
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if (!clockevent_state_oneshot(&clockevent->dev)) |
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davinci_tim12_shutdown(clockevent->base); |
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clockevent->dev.event_handler(&clockevent->dev); |
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return IRQ_HANDLED; |
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} |
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static u64 notrace davinci_timer_read_sched_clock(void) |
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{ |
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return readl_relaxed(davinci_clocksource.base + |
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davinci_clocksource.tim_off); |
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} |
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static u64 davinci_clocksource_read(struct clocksource *dev) |
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{ |
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return davinci_timer_read_sched_clock(); |
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} |
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/* |
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* Standard use-case: we're using tim12 for clockevent and tim34 for |
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* clocksource. The default is making the former run in oneshot mode |
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* and the latter in periodic mode. |
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*/ |
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static void davinci_clocksource_init_tim34(void __iomem *base) |
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{ |
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int tcr; |
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tcr = DAVINCI_TIMER_ENAMODE_PERIODIC << |
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DAVINCI_TIMER_ENAMODE_SHIFT_TIM34; |
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tcr |= DAVINCI_TIMER_ENAMODE_ONESHOT << |
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DAVINCI_TIMER_ENAMODE_SHIFT_TIM12; |
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writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34); |
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writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34); |
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writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); |
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} |
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/* |
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* Special use-case on da830: the DSP may use tim34. We're using tim12 for |
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* both clocksource and clockevent. We set tim12 to periodic and don't touch |
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* tim34. |
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*/ |
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static void davinci_clocksource_init_tim12(void __iomem *base) |
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{ |
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unsigned int tcr; |
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tcr = DAVINCI_TIMER_ENAMODE_PERIODIC << |
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DAVINCI_TIMER_ENAMODE_SHIFT_TIM12; |
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writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12); |
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writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12); |
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writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); |
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} |
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static void davinci_timer_init(void __iomem *base) |
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{ |
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/* Set clock to internal mode and disable it. */ |
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writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR); |
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/* |
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* Reset both 32-bit timers, set no prescaler for timer 34, set the |
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* timer to dual 32-bit unchained mode, unreset both 32-bit timers. |
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*/ |
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writel_relaxed(DAVINCI_TIMER_TGCR_DEFAULT, |
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base + DAVINCI_TIMER_REG_TGCR); |
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/* Init both counters to zero. */ |
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writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12); |
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writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34); |
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} |
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int __init davinci_timer_register(struct clk *clk, |
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const struct davinci_timer_cfg *timer_cfg) |
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{ |
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struct davinci_clockevent *clockevent; |
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unsigned int tick_rate; |
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void __iomem *base; |
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int rv; |
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rv = clk_prepare_enable(clk); |
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if (rv) { |
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pr_err("Unable to prepare and enable the timer clock\n"); |
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return rv; |
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} |
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if (!request_mem_region(timer_cfg->reg.start, |
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resource_size(&timer_cfg->reg), |
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"davinci-timer")) { |
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pr_err("Unable to request memory region\n"); |
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return -EBUSY; |
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} |
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base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg)); |
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if (!base) { |
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pr_err("Unable to map the register range\n"); |
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return -ENOMEM; |
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} |
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davinci_timer_init(base); |
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tick_rate = clk_get_rate(clk); |
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clockevent = kzalloc(sizeof(*clockevent), GFP_KERNEL); |
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if (!clockevent) |
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return -ENOMEM; |
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clockevent->dev.name = "tim12"; |
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clockevent->dev.features = CLOCK_EVT_FEAT_ONESHOT; |
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clockevent->dev.cpumask = cpumask_of(0); |
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clockevent->base = base; |
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if (timer_cfg->cmp_off) { |
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clockevent->cmp_off = timer_cfg->cmp_off; |
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clockevent->dev.set_next_event = |
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davinci_clockevent_set_next_event_cmp; |
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} else { |
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clockevent->dev.set_next_event = |
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davinci_clockevent_set_next_event_std; |
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clockevent->dev.set_state_oneshot = |
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davinci_clockevent_set_oneshot; |
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clockevent->dev.set_state_shutdown = |
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davinci_clockevent_shutdown; |
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} |
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rv = request_irq(timer_cfg->irq[DAVINCI_TIMER_CLOCKEVENT_IRQ].start, |
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davinci_timer_irq_timer, IRQF_TIMER, |
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"clockevent/tim12", clockevent); |
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if (rv) { |
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pr_err("Unable to request the clockevent interrupt\n"); |
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return rv; |
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} |
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davinci_clocksource.dev.rating = 300; |
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davinci_clocksource.dev.read = davinci_clocksource_read; |
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davinci_clocksource.dev.mask = |
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CLOCKSOURCE_MASK(DAVINCI_TIMER_CLKSRC_BITS); |
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davinci_clocksource.dev.flags = CLOCK_SOURCE_IS_CONTINUOUS; |
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davinci_clocksource.base = base; |
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if (timer_cfg->cmp_off) { |
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davinci_clocksource.dev.name = "tim12"; |
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davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM12; |
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davinci_clocksource_init_tim12(base); |
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} else { |
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davinci_clocksource.dev.name = "tim34"; |
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davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM34; |
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davinci_clocksource_init_tim34(base); |
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} |
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clockevents_config_and_register(&clockevent->dev, tick_rate, |
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DAVINCI_TIMER_MIN_DELTA, |
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DAVINCI_TIMER_MAX_DELTA); |
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rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate); |
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if (rv) { |
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pr_err("Unable to register clocksource\n"); |
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return rv; |
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} |
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sched_clock_register(davinci_timer_read_sched_clock, |
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DAVINCI_TIMER_CLKSRC_BITS, tick_rate); |
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return 0; |
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} |
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static int __init of_davinci_timer_register(struct device_node *np) |
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{ |
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struct davinci_timer_cfg timer_cfg = { }; |
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struct clk *clk; |
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int rv; |
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rv = of_address_to_resource(np, 0, &timer_cfg.reg); |
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if (rv) { |
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pr_err("Unable to get the register range for timer\n"); |
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return rv; |
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} |
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rv = of_irq_to_resource_table(np, timer_cfg.irq, |
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DAVINCI_TIMER_NUM_IRQS); |
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if (rv != DAVINCI_TIMER_NUM_IRQS) { |
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pr_err("Unable to get the interrupts for timer\n"); |
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return rv; |
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} |
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clk = of_clk_get(np, 0); |
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if (IS_ERR(clk)) { |
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pr_err("Unable to get the timer clock\n"); |
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return PTR_ERR(clk); |
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} |
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rv = davinci_timer_register(clk, &timer_cfg); |
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if (rv) |
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clk_put(clk); |
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return rv; |
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} |
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TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_register);
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