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244 lines
5.9 KiB
244 lines
5.9 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2020 Western Digital Corporation or its affiliates. |
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* |
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* Most of the M-mode (i.e. NoMMU) RISC-V systems usually have a |
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* CLINT MMIO timer device. |
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*/ |
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#define pr_fmt(fmt) "clint: " fmt |
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#include <linux/bitops.h> |
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#include <linux/clocksource.h> |
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#include <linux/clockchips.h> |
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#include <linux/cpu.h> |
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#include <linux/delay.h> |
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#include <linux/module.h> |
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#include <linux/of_address.h> |
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#include <linux/sched_clock.h> |
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#include <linux/io-64-nonatomic-lo-hi.h> |
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#include <linux/interrupt.h> |
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#include <linux/of_irq.h> |
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#include <linux/smp.h> |
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#include <linux/timex.h> |
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#ifndef CONFIG_RISCV_M_MODE |
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#include <asm/clint.h> |
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#endif |
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#define CLINT_IPI_OFF 0 |
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#define CLINT_TIMER_CMP_OFF 0x4000 |
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#define CLINT_TIMER_VAL_OFF 0xbff8 |
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/* CLINT manages IPI and Timer for RISC-V M-mode */ |
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static u32 __iomem *clint_ipi_base; |
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static u64 __iomem *clint_timer_cmp; |
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static u64 __iomem *clint_timer_val; |
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static unsigned long clint_timer_freq; |
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static unsigned int clint_timer_irq; |
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#ifdef CONFIG_RISCV_M_MODE |
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u64 __iomem *clint_time_val; |
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EXPORT_SYMBOL(clint_time_val); |
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#endif |
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static void clint_send_ipi(const struct cpumask *target) |
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{ |
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unsigned int cpu; |
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for_each_cpu(cpu, target) |
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writel(1, clint_ipi_base + cpuid_to_hartid_map(cpu)); |
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} |
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static void clint_clear_ipi(void) |
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{ |
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writel(0, clint_ipi_base + cpuid_to_hartid_map(smp_processor_id())); |
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} |
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static struct riscv_ipi_ops clint_ipi_ops = { |
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.ipi_inject = clint_send_ipi, |
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.ipi_clear = clint_clear_ipi, |
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}; |
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#ifdef CONFIG_64BIT |
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#define clint_get_cycles() readq_relaxed(clint_timer_val) |
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#else |
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#define clint_get_cycles() readl_relaxed(clint_timer_val) |
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#define clint_get_cycles_hi() readl_relaxed(((u32 *)clint_timer_val) + 1) |
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#endif |
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#ifdef CONFIG_64BIT |
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static u64 notrace clint_get_cycles64(void) |
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{ |
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return clint_get_cycles(); |
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} |
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#else /* CONFIG_64BIT */ |
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static u64 notrace clint_get_cycles64(void) |
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{ |
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u32 hi, lo; |
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do { |
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hi = clint_get_cycles_hi(); |
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lo = clint_get_cycles(); |
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} while (hi != clint_get_cycles_hi()); |
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return ((u64)hi << 32) | lo; |
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} |
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#endif /* CONFIG_64BIT */ |
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static u64 clint_rdtime(struct clocksource *cs) |
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{ |
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return clint_get_cycles64(); |
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} |
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static struct clocksource clint_clocksource = { |
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.name = "clint_clocksource", |
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.rating = 300, |
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.mask = CLOCKSOURCE_MASK(64), |
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.flags = CLOCK_SOURCE_IS_CONTINUOUS, |
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.read = clint_rdtime, |
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}; |
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static int clint_clock_next_event(unsigned long delta, |
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struct clock_event_device *ce) |
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{ |
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void __iomem *r = clint_timer_cmp + |
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cpuid_to_hartid_map(smp_processor_id()); |
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csr_set(CSR_IE, IE_TIE); |
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writeq_relaxed(clint_get_cycles64() + delta, r); |
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return 0; |
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} |
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static DEFINE_PER_CPU(struct clock_event_device, clint_clock_event) = { |
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.name = "clint_clockevent", |
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.features = CLOCK_EVT_FEAT_ONESHOT, |
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.rating = 100, |
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.set_next_event = clint_clock_next_event, |
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}; |
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static int clint_timer_starting_cpu(unsigned int cpu) |
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{ |
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struct clock_event_device *ce = per_cpu_ptr(&clint_clock_event, cpu); |
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ce->cpumask = cpumask_of(cpu); |
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clockevents_config_and_register(ce, clint_timer_freq, 100, 0x7fffffff); |
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enable_percpu_irq(clint_timer_irq, |
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irq_get_trigger_type(clint_timer_irq)); |
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return 0; |
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} |
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static int clint_timer_dying_cpu(unsigned int cpu) |
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{ |
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disable_percpu_irq(clint_timer_irq); |
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return 0; |
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} |
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static irqreturn_t clint_timer_interrupt(int irq, void *dev_id) |
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{ |
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struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event); |
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csr_clear(CSR_IE, IE_TIE); |
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evdev->event_handler(evdev); |
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return IRQ_HANDLED; |
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} |
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static int __init clint_timer_init_dt(struct device_node *np) |
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{ |
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int rc; |
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u32 i, nr_irqs; |
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void __iomem *base; |
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struct of_phandle_args oirq; |
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/* |
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* Ensure that CLINT device interrupts are either RV_IRQ_TIMER or |
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* RV_IRQ_SOFT. If it's anything else then we ignore the device. |
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*/ |
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nr_irqs = of_irq_count(np); |
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for (i = 0; i < nr_irqs; i++) { |
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if (of_irq_parse_one(np, i, &oirq)) { |
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pr_err("%pOFP: failed to parse irq %d.\n", np, i); |
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continue; |
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} |
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if ((oirq.args_count != 1) || |
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(oirq.args[0] != RV_IRQ_TIMER && |
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oirq.args[0] != RV_IRQ_SOFT)) { |
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pr_err("%pOFP: invalid irq %d (hwirq %d)\n", |
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np, i, oirq.args[0]); |
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return -ENODEV; |
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} |
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/* Find parent irq domain and map timer irq */ |
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if (!clint_timer_irq && |
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oirq.args[0] == RV_IRQ_TIMER && |
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irq_find_host(oirq.np)) |
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clint_timer_irq = irq_of_parse_and_map(np, i); |
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} |
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/* If CLINT timer irq not found then fail */ |
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if (!clint_timer_irq) { |
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pr_err("%pOFP: timer irq not found\n", np); |
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return -ENODEV; |
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} |
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base = of_iomap(np, 0); |
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if (!base) { |
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pr_err("%pOFP: could not map registers\n", np); |
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return -ENODEV; |
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} |
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clint_ipi_base = base + CLINT_IPI_OFF; |
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clint_timer_cmp = base + CLINT_TIMER_CMP_OFF; |
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clint_timer_val = base + CLINT_TIMER_VAL_OFF; |
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clint_timer_freq = riscv_timebase; |
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#ifdef CONFIG_RISCV_M_MODE |
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/* |
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* Yes, that's an odd naming scheme. time_val is public, but hopefully |
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* will die in favor of something cleaner. |
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*/ |
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clint_time_val = clint_timer_val; |
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#endif |
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pr_info("%pOFP: timer running at %ld Hz\n", np, clint_timer_freq); |
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rc = clocksource_register_hz(&clint_clocksource, clint_timer_freq); |
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if (rc) { |
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pr_err("%pOFP: clocksource register failed [%d]\n", np, rc); |
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goto fail_iounmap; |
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} |
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sched_clock_register(clint_get_cycles64, 64, clint_timer_freq); |
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rc = request_percpu_irq(clint_timer_irq, clint_timer_interrupt, |
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"clint-timer", &clint_clock_event); |
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if (rc) { |
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pr_err("registering percpu irq failed [%d]\n", rc); |
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goto fail_iounmap; |
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} |
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rc = cpuhp_setup_state(CPUHP_AP_CLINT_TIMER_STARTING, |
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"clockevents/clint/timer:starting", |
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clint_timer_starting_cpu, |
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clint_timer_dying_cpu); |
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if (rc) { |
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pr_err("%pOFP: cpuhp setup state failed [%d]\n", np, rc); |
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goto fail_free_irq; |
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} |
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riscv_set_ipi_ops(&clint_ipi_ops); |
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clint_clear_ipi(); |
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return 0; |
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fail_free_irq: |
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free_irq(clint_timer_irq, &clint_clock_event); |
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fail_iounmap: |
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iounmap(base); |
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return rc; |
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} |
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TIMER_OF_DECLARE(clint_timer, "riscv,clint0", clint_timer_init_dt); |
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TIMER_OF_DECLARE(clint_timer1, "sifive,clint0", clint_timer_init_dt);
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