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177 lines
4.2 KiB
177 lines
4.2 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (C) 2015 Altera Corporation. All rights reserved |
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*/ |
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#include <linux/slab.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/of.h> |
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#include <linux/regmap.h> |
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#include "clk.h" |
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#define streq(a, b) (strcmp((a), (b)) == 0) |
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#define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) |
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/* SDMMC Group for System Manager defines */ |
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#define SYSMGR_SDMMCGRP_CTRL_OFFSET 0x28 |
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static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk, |
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unsigned long parent_rate) |
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{ |
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); |
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u32 div = 1, val; |
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if (socfpgaclk->fixed_div) |
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div = socfpgaclk->fixed_div; |
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else if (socfpgaclk->div_reg) { |
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val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; |
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val &= GENMASK(socfpgaclk->width - 1, 0); |
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div = (1 << val); |
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} |
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return parent_rate / div; |
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} |
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static int socfpga_clk_prepare(struct clk_hw *hwclk) |
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{ |
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struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); |
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int i; |
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u32 hs_timing; |
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u32 clk_phase[2]; |
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if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { |
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for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { |
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switch (socfpgaclk->clk_phase[i]) { |
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case 0: |
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clk_phase[i] = 0; |
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break; |
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case 45: |
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clk_phase[i] = 1; |
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break; |
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case 90: |
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clk_phase[i] = 2; |
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break; |
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case 135: |
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clk_phase[i] = 3; |
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break; |
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case 180: |
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clk_phase[i] = 4; |
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break; |
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case 225: |
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clk_phase[i] = 5; |
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break; |
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case 270: |
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clk_phase[i] = 6; |
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break; |
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case 315: |
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clk_phase[i] = 7; |
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break; |
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default: |
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clk_phase[i] = 0; |
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break; |
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} |
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} |
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hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]); |
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if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) |
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regmap_write(socfpgaclk->sys_mgr_base_addr, |
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SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing); |
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else |
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pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n", |
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__func__); |
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} |
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return 0; |
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} |
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static struct clk_ops gateclk_ops = { |
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.prepare = socfpga_clk_prepare, |
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.recalc_rate = socfpga_gate_clk_recalc_rate, |
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}; |
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static void __init __socfpga_gate_init(struct device_node *node, |
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const struct clk_ops *ops) |
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{ |
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u32 clk_gate[2]; |
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u32 div_reg[3]; |
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u32 clk_phase[2]; |
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u32 fixed_div; |
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struct clk *clk; |
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struct socfpga_gate_clk *socfpga_clk; |
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const char *clk_name = node->name; |
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const char *parent_name[SOCFPGA_MAX_PARENTS]; |
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struct clk_init_data init; |
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int rc; |
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socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); |
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if (WARN_ON(!socfpga_clk)) |
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return; |
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rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2); |
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if (rc) |
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clk_gate[0] = 0; |
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if (clk_gate[0]) { |
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socfpga_clk->hw.reg = clk_mgr_a10_base_addr + clk_gate[0]; |
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socfpga_clk->hw.bit_idx = clk_gate[1]; |
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gateclk_ops.enable = clk_gate_ops.enable; |
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gateclk_ops.disable = clk_gate_ops.disable; |
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} |
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rc = of_property_read_u32(node, "fixed-divider", &fixed_div); |
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if (rc) |
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socfpga_clk->fixed_div = 0; |
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else |
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socfpga_clk->fixed_div = fixed_div; |
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rc = of_property_read_u32_array(node, "div-reg", div_reg, 3); |
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if (!rc) { |
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socfpga_clk->div_reg = clk_mgr_a10_base_addr + div_reg[0]; |
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socfpga_clk->shift = div_reg[1]; |
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socfpga_clk->width = div_reg[2]; |
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} else { |
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socfpga_clk->div_reg = NULL; |
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} |
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rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); |
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if (!rc) { |
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socfpga_clk->clk_phase[0] = clk_phase[0]; |
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socfpga_clk->clk_phase[1] = clk_phase[1]; |
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socfpga_clk->sys_mgr_base_addr = |
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syscon_regmap_lookup_by_compatible("altr,sys-mgr"); |
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if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) { |
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pr_err("%s: failed to find altr,sys-mgr regmap!\n", |
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__func__); |
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kfree(socfpga_clk); |
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return; |
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} |
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} |
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of_property_read_string(node, "clock-output-names", &clk_name); |
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init.name = clk_name; |
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init.ops = ops; |
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init.flags = 0; |
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init.num_parents = of_clk_parent_fill(node, parent_name, SOCFPGA_MAX_PARENTS); |
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init.parent_names = parent_name; |
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socfpga_clk->hw.hw.init = &init; |
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clk = clk_register(NULL, &socfpga_clk->hw.hw); |
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if (WARN_ON(IS_ERR(clk))) { |
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kfree(socfpga_clk); |
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return; |
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} |
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rc = of_clk_add_provider(node, of_clk_src_simple_get, clk); |
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if (WARN_ON(rc)) |
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return; |
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} |
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void __init socfpga_a10_gate_init(struct device_node *node) |
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{ |
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__socfpga_gate_init(node, &gateclk_ops); |
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}
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