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139 lines
3.3 KiB
139 lines
3.3 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (c) 2016 Rockchip Electronics Co. Ltd. |
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* Author: Lin Huang <[email protected]> |
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*/ |
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#include <linux/arm-smccc.h> |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/slab.h> |
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#include <soc/rockchip/rockchip_sip.h> |
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#include "clk.h" |
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struct rockchip_ddrclk { |
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struct clk_hw hw; |
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void __iomem *reg_base; |
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int mux_offset; |
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int mux_shift; |
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int mux_width; |
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int div_shift; |
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int div_width; |
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int ddr_flag; |
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spinlock_t *lock; |
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}; |
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#define to_rockchip_ddrclk_hw(hw) container_of(hw, struct rockchip_ddrclk, hw) |
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static int rockchip_ddrclk_sip_set_rate(struct clk_hw *hw, unsigned long drate, |
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unsigned long prate) |
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{ |
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struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw); |
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unsigned long flags; |
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struct arm_smccc_res res; |
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spin_lock_irqsave(ddrclk->lock, flags); |
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arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, drate, 0, |
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ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE, |
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0, 0, 0, 0, &res); |
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spin_unlock_irqrestore(ddrclk->lock, flags); |
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return res.a0; |
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} |
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static unsigned long |
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rockchip_ddrclk_sip_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct arm_smccc_res res; |
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arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0, |
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ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE, |
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0, 0, 0, 0, &res); |
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return res.a0; |
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} |
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static long rockchip_ddrclk_sip_round_rate(struct clk_hw *hw, |
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unsigned long rate, |
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unsigned long *prate) |
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{ |
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struct arm_smccc_res res; |
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arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, rate, 0, |
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ROCKCHIP_SIP_CONFIG_DRAM_ROUND_RATE, |
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0, 0, 0, 0, &res); |
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return res.a0; |
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} |
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static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw) |
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{ |
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struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw); |
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u32 val; |
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val = readl(ddrclk->reg_base + |
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ddrclk->mux_offset) >> ddrclk->mux_shift; |
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val &= GENMASK(ddrclk->mux_width - 1, 0); |
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return val; |
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} |
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static const struct clk_ops rockchip_ddrclk_sip_ops = { |
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.recalc_rate = rockchip_ddrclk_sip_recalc_rate, |
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.set_rate = rockchip_ddrclk_sip_set_rate, |
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.round_rate = rockchip_ddrclk_sip_round_rate, |
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.get_parent = rockchip_ddrclk_get_parent, |
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}; |
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struct clk *rockchip_clk_register_ddrclk(const char *name, int flags, |
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const char *const *parent_names, |
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u8 num_parents, int mux_offset, |
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int mux_shift, int mux_width, |
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int div_shift, int div_width, |
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int ddr_flag, void __iomem *reg_base, |
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spinlock_t *lock) |
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{ |
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struct rockchip_ddrclk *ddrclk; |
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struct clk_init_data init; |
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struct clk *clk; |
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ddrclk = kzalloc(sizeof(*ddrclk), GFP_KERNEL); |
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if (!ddrclk) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.parent_names = parent_names; |
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init.num_parents = num_parents; |
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init.flags = flags; |
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init.flags |= CLK_SET_RATE_NO_REPARENT; |
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switch (ddr_flag) { |
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case ROCKCHIP_DDRCLK_SIP: |
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init.ops = &rockchip_ddrclk_sip_ops; |
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break; |
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default: |
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pr_err("%s: unsupported ddrclk type %d\n", __func__, ddr_flag); |
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kfree(ddrclk); |
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return ERR_PTR(-EINVAL); |
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} |
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ddrclk->reg_base = reg_base; |
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ddrclk->lock = lock; |
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ddrclk->hw.init = &init; |
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ddrclk->mux_offset = mux_offset; |
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ddrclk->mux_shift = mux_shift; |
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ddrclk->mux_width = mux_width; |
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ddrclk->div_shift = div_shift; |
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ddrclk->div_width = div_width; |
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ddrclk->ddr_flag = ddr_flag; |
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clk = clk_register(NULL, &ddrclk->hw); |
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if (IS_ERR(clk)) |
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kfree(ddrclk); |
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return clk; |
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} |
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EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);
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