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201 lines
4.5 KiB
201 lines
4.5 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Marvell Dove SoC clocks |
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* |
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* Copyright (C) 2012 Marvell |
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* |
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* Gregory CLEMENT <[email protected]> |
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* Sebastian Hesselbarth <[email protected]> |
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* Andrew Lunn <[email protected]> |
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* |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include "common.h" |
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#include "dove-divider.h" |
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/* |
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* Core Clocks |
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* |
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* Dove PLL sample-at-reset configuration |
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* |
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* SAR0[8:5] : CPU frequency |
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* 5 = 1000 MHz |
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* 6 = 933 MHz |
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* 7 = 933 MHz |
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* 8 = 800 MHz |
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* 9 = 800 MHz |
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* 10 = 800 MHz |
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* 11 = 1067 MHz |
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* 12 = 667 MHz |
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* 13 = 533 MHz |
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* 14 = 400 MHz |
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* 15 = 333 MHz |
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* others reserved. |
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* |
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* SAR0[11:9] : CPU to L2 Clock divider ratio |
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* 0 = (1/1) * CPU |
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* 2 = (1/2) * CPU |
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* 4 = (1/3) * CPU |
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* 6 = (1/4) * CPU |
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* others reserved. |
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* |
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* SAR0[15:12] : CPU to DDR DRAM Clock divider ratio |
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* 0 = (1/1) * CPU |
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* 2 = (1/2) * CPU |
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* 3 = (2/5) * CPU |
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* 4 = (1/3) * CPU |
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* 6 = (1/4) * CPU |
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* 8 = (1/5) * CPU |
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* 10 = (1/6) * CPU |
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* 12 = (1/7) * CPU |
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* 14 = (1/8) * CPU |
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* 15 = (1/10) * CPU |
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* others reserved. |
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* |
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* SAR0[24:23] : TCLK frequency |
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* 0 = 166 MHz |
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* 1 = 125 MHz |
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* others reserved. |
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*/ |
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#define SAR_DOVE_CPU_FREQ 5 |
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#define SAR_DOVE_CPU_FREQ_MASK 0xf |
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#define SAR_DOVE_L2_RATIO 9 |
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#define SAR_DOVE_L2_RATIO_MASK 0x7 |
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#define SAR_DOVE_DDR_RATIO 12 |
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#define SAR_DOVE_DDR_RATIO_MASK 0xf |
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#define SAR_DOVE_TCLK_FREQ 23 |
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#define SAR_DOVE_TCLK_FREQ_MASK 0x3 |
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enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR }; |
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static const struct coreclk_ratio dove_coreclk_ratios[] __initconst = { |
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{ .id = DOVE_CPU_TO_L2, .name = "l2clk", }, |
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{ .id = DOVE_CPU_TO_DDR, .name = "ddrclk", } |
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}; |
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static const u32 dove_tclk_freqs[] __initconst = { |
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166666667, |
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125000000, |
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0, 0 |
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}; |
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static u32 __init dove_get_tclk_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) & |
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SAR_DOVE_TCLK_FREQ_MASK; |
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return dove_tclk_freqs[opt]; |
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} |
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static const u32 dove_cpu_freqs[] __initconst = { |
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0, 0, 0, 0, 0, |
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1000000000, |
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933333333, 933333333, |
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800000000, 800000000, 800000000, |
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1066666667, |
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666666667, |
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533333333, |
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400000000, |
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333333333 |
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}; |
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static u32 __init dove_get_cpu_freq(void __iomem *sar) |
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{ |
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u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) & |
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SAR_DOVE_CPU_FREQ_MASK; |
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return dove_cpu_freqs[opt]; |
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} |
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static const int dove_cpu_l2_ratios[8][2] __initconst = { |
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{ 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 }, |
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{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 } |
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}; |
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static const int dove_cpu_ddr_ratios[16][2] __initconst = { |
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{ 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 }, |
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{ 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }, |
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{ 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 }, |
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{ 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 } |
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}; |
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static void __init dove_get_clk_ratio( |
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void __iomem *sar, int id, int *mult, int *div) |
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{ |
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switch (id) { |
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case DOVE_CPU_TO_L2: |
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{ |
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u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) & |
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SAR_DOVE_L2_RATIO_MASK; |
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*mult = dove_cpu_l2_ratios[opt][0]; |
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*div = dove_cpu_l2_ratios[opt][1]; |
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break; |
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} |
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case DOVE_CPU_TO_DDR: |
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{ |
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u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) & |
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SAR_DOVE_DDR_RATIO_MASK; |
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*mult = dove_cpu_ddr_ratios[opt][0]; |
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*div = dove_cpu_ddr_ratios[opt][1]; |
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break; |
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} |
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} |
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} |
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static const struct coreclk_soc_desc dove_coreclks = { |
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.get_tclk_freq = dove_get_tclk_freq, |
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.get_cpu_freq = dove_get_cpu_freq, |
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.get_clk_ratio = dove_get_clk_ratio, |
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.ratios = dove_coreclk_ratios, |
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.num_ratios = ARRAY_SIZE(dove_coreclk_ratios), |
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}; |
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/* |
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* Clock Gating Control |
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*/ |
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static const struct clk_gating_soc_desc dove_gating_desc[] __initconst = { |
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{ "usb0", NULL, 0, 0 }, |
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{ "usb1", NULL, 1, 0 }, |
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{ "ge", "gephy", 2, 0 }, |
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{ "sata", NULL, 3, 0 }, |
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{ "pex0", NULL, 4, 0 }, |
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{ "pex1", NULL, 5, 0 }, |
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{ "sdio0", NULL, 8, 0 }, |
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{ "sdio1", NULL, 9, 0 }, |
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{ "nand", NULL, 10, 0 }, |
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{ "camera", NULL, 11, 0 }, |
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{ "i2s0", NULL, 12, 0 }, |
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{ "i2s1", NULL, 13, 0 }, |
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{ "crypto", NULL, 15, 0 }, |
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{ "ac97", NULL, 21, 0 }, |
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{ "pdma", NULL, 22, 0 }, |
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{ "xor0", NULL, 23, 0 }, |
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{ "xor1", NULL, 24, 0 }, |
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{ "gephy", NULL, 30, 0 }, |
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{ } |
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}; |
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static void __init dove_clk_init(struct device_node *np) |
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{ |
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struct device_node *cgnp = |
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of_find_compatible_node(NULL, NULL, "marvell,dove-gating-clock"); |
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struct device_node *ddnp = |
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of_find_compatible_node(NULL, NULL, "marvell,dove-divider-clock"); |
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mvebu_coreclk_setup(np, &dove_coreclks); |
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if (ddnp) { |
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dove_divider_clk_init(ddnp); |
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of_node_put(ddnp); |
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} |
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if (cgnp) { |
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mvebu_clk_gating_setup(cgnp, dove_gating_desc); |
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of_node_put(cgnp); |
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} |
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} |
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CLK_OF_DECLARE(dove_clk, "marvell,dove-core-clock", dove_clk_init);
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