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118 lines
3.9 KiB
118 lines
3.9 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Copyright (c) 2012-2016 Zhang, Keguang <[email protected]> |
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*/ |
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#include <linux/clkdev.h> |
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#include <linux/clk-provider.h> |
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#include <linux/io.h> |
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#include <linux/err.h> |
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#include <loongson1.h> |
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#include "clk.h" |
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#define OSC (33 * 1000000) |
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#define DIV_APB 2 |
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static DEFINE_SPINLOCK(_lock); |
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static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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u32 pll, rate; |
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pll = __raw_readl(LS1X_CLK_PLL_FREQ); |
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rate = 12 + (pll & GENMASK(5, 0)); |
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rate *= OSC; |
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rate >>= 1; |
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return rate; |
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} |
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static const struct clk_ops ls1x_pll_clk_ops = { |
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.recalc_rate = ls1x_pll_recalc_rate, |
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}; |
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static const char *const cpu_parents[] = { "cpu_clk_div", "osc_clk", }; |
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static const char *const ahb_parents[] = { "ahb_clk_div", "osc_clk", }; |
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static const char *const dc_parents[] = { "dc_clk_div", "osc_clk", }; |
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void __init ls1x_clk_init(void) |
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{ |
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struct clk_hw *hw; |
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hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC); |
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clk_hw_register_clkdev(hw, "osc_clk", NULL); |
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/* clock derived from 33 MHz OSC clk */ |
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hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk", |
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&ls1x_pll_clk_ops, 0); |
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clk_hw_register_clkdev(hw, "pll_clk", NULL); |
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/* clock derived from PLL clk */ |
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/* _____ |
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* _______________________| | |
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* OSC ___/ | MUX |___ CPU CLK |
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* \___ PLL ___ CPU DIV ___| | |
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* |_____| |
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*/ |
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hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk", |
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CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV, |
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DIV_CPU_SHIFT, DIV_CPU_WIDTH, |
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CLK_DIVIDER_ONE_BASED | |
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CLK_DIVIDER_ROUND_CLOSEST, &_lock); |
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clk_hw_register_clkdev(hw, "cpu_clk_div", NULL); |
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hw = clk_hw_register_mux(NULL, "cpu_clk", cpu_parents, |
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ARRAY_SIZE(cpu_parents), |
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CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV, |
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BYPASS_CPU_SHIFT, BYPASS_CPU_WIDTH, 0, &_lock); |
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clk_hw_register_clkdev(hw, "cpu_clk", NULL); |
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/* _____ |
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* _______________________| | |
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* OSC ___/ | MUX |___ DC CLK |
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* \___ PLL ___ DC DIV ___| | |
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* |_____| |
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*/ |
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hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk", |
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0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT, |
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DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock); |
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clk_hw_register_clkdev(hw, "dc_clk_div", NULL); |
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hw = clk_hw_register_mux(NULL, "dc_clk", dc_parents, |
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ARRAY_SIZE(dc_parents), |
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CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV, |
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BYPASS_DC_SHIFT, BYPASS_DC_WIDTH, 0, &_lock); |
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clk_hw_register_clkdev(hw, "dc_clk", NULL); |
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/* _____ |
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* _______________________| | |
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* OSC ___/ | MUX |___ DDR CLK |
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* \___ PLL ___ DDR DIV ___| | |
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* |_____| |
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*/ |
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hw = clk_hw_register_divider(NULL, "ahb_clk_div", "pll_clk", |
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0, LS1X_CLK_PLL_DIV, DIV_DDR_SHIFT, |
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DIV_DDR_WIDTH, CLK_DIVIDER_ONE_BASED, |
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&_lock); |
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clk_hw_register_clkdev(hw, "ahb_clk_div", NULL); |
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hw = clk_hw_register_mux(NULL, "ahb_clk", ahb_parents, |
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ARRAY_SIZE(ahb_parents), |
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CLK_SET_RATE_NO_REPARENT, LS1X_CLK_PLL_DIV, |
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BYPASS_DDR_SHIFT, BYPASS_DDR_WIDTH, 0, &_lock); |
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clk_hw_register_clkdev(hw, "ahb_clk", NULL); |
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clk_hw_register_clkdev(hw, "ls1x-dma", NULL); |
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clk_hw_register_clkdev(hw, "stmmaceth", NULL); |
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/* clock derived from AHB clk */ |
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/* APB clk is always half of the AHB clk */ |
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hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1, |
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DIV_APB); |
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clk_hw_register_clkdev(hw, "apb_clk", NULL); |
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clk_hw_register_clkdev(hw, "ls1x-ac97", NULL); |
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clk_hw_register_clkdev(hw, "ls1x-i2c", NULL); |
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clk_hw_register_clkdev(hw, "ls1x-nand", NULL); |
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clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL); |
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clk_hw_register_clkdev(hw, "ls1x-spi", NULL); |
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clk_hw_register_clkdev(hw, "ls1x-wdt", NULL); |
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clk_hw_register_clkdev(hw, "serial8250", NULL); |
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}
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