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663 lines
17 KiB
663 lines
17 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Copyright (C) 2018 Socionext Inc. |
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* Copyright (C) 2016 Linaro Ltd. |
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*/ |
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#include <linux/clk-provider.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/iopoll.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/spinlock.h> |
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#define M10V_CLKSEL1 0x0 |
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#define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1) |
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#define M10V_PLL1 "pll1" |
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#define M10V_PLL1DIV2 "pll1-2" |
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#define M10V_PLL2 "pll2" |
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#define M10V_PLL2DIV2 "pll2-2" |
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#define M10V_PLL6 "pll6" |
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#define M10V_PLL6DIV2 "pll6-2" |
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#define M10V_PLL6DIV3 "pll6-3" |
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#define M10V_PLL7 "pll7" |
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#define M10V_PLL7DIV2 "pll7-2" |
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#define M10V_PLL7DIV5 "pll7-5" |
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#define M10V_PLL9 "pll9" |
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#define M10V_PLL10 "pll10" |
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#define M10V_PLL10DIV2 "pll10-2" |
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#define M10V_PLL11 "pll11" |
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#define M10V_SPI_PARENT0 "spi-parent0" |
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#define M10V_SPI_PARENT1 "spi-parent1" |
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#define M10V_SPI_PARENT2 "spi-parent2" |
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#define M10V_UHS1CLK2_PARENT0 "uhs1clk2-parent0" |
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#define M10V_UHS1CLK2_PARENT1 "uhs1clk2-parent1" |
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#define M10V_UHS1CLK2_PARENT2 "uhs1clk2-parent2" |
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#define M10V_UHS1CLK1_PARENT0 "uhs1clk1-parent0" |
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#define M10V_UHS1CLK1_PARENT1 "uhs1clk1-parent1" |
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#define M10V_NFCLK_PARENT0 "nfclk-parent0" |
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#define M10V_NFCLK_PARENT1 "nfclk-parent1" |
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#define M10V_NFCLK_PARENT2 "nfclk-parent2" |
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#define M10V_NFCLK_PARENT3 "nfclk-parent3" |
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#define M10V_NFCLK_PARENT4 "nfclk-parent4" |
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#define M10V_NFCLK_PARENT5 "nfclk-parent5" |
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#define M10V_DCHREQ 1 |
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#define M10V_UPOLL_RATE 1 |
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#define M10V_UTIMEOUT 250 |
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#define M10V_EMMCCLK_ID 0 |
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#define M10V_ACLK_ID 1 |
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#define M10V_HCLK_ID 2 |
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#define M10V_PCLK_ID 3 |
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#define M10V_RCLK_ID 4 |
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#define M10V_SPICLK_ID 5 |
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#define M10V_NFCLK_ID 6 |
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#define M10V_UHS1CLK2_ID 7 |
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#define M10V_NUM_CLKS 8 |
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#define to_m10v_div(_hw) container_of(_hw, struct m10v_clk_divider, hw) |
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static struct clk_hw_onecell_data *m10v_clk_data; |
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static DEFINE_SPINLOCK(m10v_crglock); |
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struct m10v_clk_div_factors { |
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const char *name; |
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const char *parent_name; |
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u32 offset; |
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u8 shift; |
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u8 width; |
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const struct clk_div_table *table; |
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unsigned long div_flags; |
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int onecell_idx; |
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}; |
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struct m10v_clk_div_fixed_data { |
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const char *name; |
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const char *parent_name; |
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u8 div; |
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u8 mult; |
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int onecell_idx; |
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}; |
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struct m10v_clk_mux_factors { |
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const char *name; |
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const char * const *parent_names; |
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u8 num_parents; |
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u32 offset; |
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u8 shift; |
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u8 mask; |
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u32 *table; |
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unsigned long mux_flags; |
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int onecell_idx; |
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}; |
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static const struct clk_div_table emmcclk_table[] = { |
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{ .val = 0, .div = 8 }, |
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{ .val = 1, .div = 9 }, |
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{ .val = 2, .div = 10 }, |
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{ .val = 3, .div = 15 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table mclk400_table[] = { |
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{ .val = 1, .div = 2 }, |
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{ .val = 3, .div = 4 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table mclk200_table[] = { |
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{ .val = 3, .div = 4 }, |
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{ .val = 7, .div = 8 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table aclk400_table[] = { |
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{ .val = 1, .div = 2 }, |
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{ .val = 3, .div = 4 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table aclk300_table[] = { |
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{ .val = 0, .div = 2 }, |
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{ .val = 1, .div = 3 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table aclk_table[] = { |
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{ .val = 3, .div = 4 }, |
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{ .val = 7, .div = 8 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table aclkexs_table[] = { |
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{ .val = 3, .div = 4 }, |
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{ .val = 4, .div = 5 }, |
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{ .val = 5, .div = 6 }, |
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{ .val = 7, .div = 8 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table hclk_table[] = { |
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{ .val = 7, .div = 8 }, |
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{ .val = 15, .div = 16 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table hclkbmh_table[] = { |
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{ .val = 3, .div = 4 }, |
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{ .val = 7, .div = 8 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table pclk_table[] = { |
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{ .val = 15, .div = 16 }, |
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{ .val = 31, .div = 32 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table rclk_table[] = { |
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{ .val = 0, .div = 8 }, |
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{ .val = 1, .div = 16 }, |
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{ .val = 2, .div = 24 }, |
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{ .val = 3, .div = 32 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table uhs1clk0_table[] = { |
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{ .val = 0, .div = 2 }, |
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{ .val = 1, .div = 3 }, |
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{ .val = 2, .div = 4 }, |
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{ .val = 3, .div = 8 }, |
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{ .val = 4, .div = 16 }, |
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{ .div = 0 }, |
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}; |
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static const struct clk_div_table uhs2clk_table[] = { |
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{ .val = 0, .div = 9 }, |
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{ .val = 1, .div = 10 }, |
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{ .val = 2, .div = 11 }, |
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{ .val = 3, .div = 12 }, |
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{ .val = 4, .div = 13 }, |
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{ .val = 5, .div = 14 }, |
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{ .val = 6, .div = 16 }, |
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{ .val = 7, .div = 18 }, |
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{ .div = 0 }, |
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}; |
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static u32 spi_mux_table[] = {0, 1, 2}; |
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static const char * const spi_mux_names[] = { |
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M10V_SPI_PARENT0, M10V_SPI_PARENT1, M10V_SPI_PARENT2 |
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}; |
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static u32 uhs1clk2_mux_table[] = {2, 3, 4, 8}; |
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static const char * const uhs1clk2_mux_names[] = { |
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M10V_UHS1CLK2_PARENT0, M10V_UHS1CLK2_PARENT1, |
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M10V_UHS1CLK2_PARENT2, M10V_PLL6DIV2 |
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}; |
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static u32 uhs1clk1_mux_table[] = {3, 4, 8}; |
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static const char * const uhs1clk1_mux_names[] = { |
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M10V_UHS1CLK1_PARENT0, M10V_UHS1CLK1_PARENT1, M10V_PLL6DIV2 |
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}; |
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static u32 nfclk_mux_table[] = {0, 1, 2, 3, 4, 8}; |
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static const char * const nfclk_mux_names[] = { |
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M10V_NFCLK_PARENT0, M10V_NFCLK_PARENT1, M10V_NFCLK_PARENT2, |
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M10V_NFCLK_PARENT3, M10V_NFCLK_PARENT4, M10V_NFCLK_PARENT5 |
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}; |
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static const struct m10v_clk_div_fixed_data m10v_pll_fixed_data[] = { |
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{M10V_PLL1, NULL, 1, 40, -1}, |
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{M10V_PLL2, NULL, 1, 30, -1}, |
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{M10V_PLL6, NULL, 1, 35, -1}, |
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{M10V_PLL7, NULL, 1, 40, -1}, |
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{M10V_PLL9, NULL, 1, 33, -1}, |
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{M10V_PLL10, NULL, 5, 108, -1}, |
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{M10V_PLL10DIV2, M10V_PLL10, 2, 1, -1}, |
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{M10V_PLL11, NULL, 2, 75, -1}, |
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}; |
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static const struct m10v_clk_div_fixed_data m10v_div_fixed_data[] = { |
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{"usb2", NULL, 2, 1, -1}, |
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{"pcisuppclk", NULL, 20, 1, -1}, |
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{M10V_PLL1DIV2, M10V_PLL1, 2, 1, -1}, |
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{M10V_PLL2DIV2, M10V_PLL2, 2, 1, -1}, |
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{M10V_PLL6DIV2, M10V_PLL6, 2, 1, -1}, |
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{M10V_PLL6DIV3, M10V_PLL6, 3, 1, -1}, |
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{M10V_PLL7DIV2, M10V_PLL7, 2, 1, -1}, |
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{M10V_PLL7DIV5, M10V_PLL7, 5, 1, -1}, |
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{"ca7wd", M10V_PLL2DIV2, 12, 1, -1}, |
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{"pclkca7wd", M10V_PLL1DIV2, 16, 1, -1}, |
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{M10V_SPI_PARENT0, M10V_PLL10DIV2, 2, 1, -1}, |
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{M10V_SPI_PARENT1, M10V_PLL10DIV2, 4, 1, -1}, |
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{M10V_SPI_PARENT2, M10V_PLL7DIV2, 8, 1, -1}, |
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{M10V_UHS1CLK2_PARENT0, M10V_PLL7, 4, 1, -1}, |
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{M10V_UHS1CLK2_PARENT1, M10V_PLL7, 8, 1, -1}, |
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{M10V_UHS1CLK2_PARENT2, M10V_PLL7, 16, 1, -1}, |
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{M10V_UHS1CLK1_PARENT0, M10V_PLL7, 8, 1, -1}, |
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{M10V_UHS1CLK1_PARENT1, M10V_PLL7, 16, 1, -1}, |
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{M10V_NFCLK_PARENT0, M10V_PLL7DIV2, 8, 1, -1}, |
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{M10V_NFCLK_PARENT1, M10V_PLL7DIV2, 10, 1, -1}, |
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{M10V_NFCLK_PARENT2, M10V_PLL7DIV2, 13, 1, -1}, |
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{M10V_NFCLK_PARENT3, M10V_PLL7DIV2, 16, 1, -1}, |
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{M10V_NFCLK_PARENT4, M10V_PLL7DIV2, 40, 1, -1}, |
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{M10V_NFCLK_PARENT5, M10V_PLL7DIV5, 10, 1, -1}, |
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}; |
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static const struct m10v_clk_div_factors m10v_div_factor_data[] = { |
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{"emmc", M10V_PLL11, CLKSEL(1), 28, 3, emmcclk_table, 0, |
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M10V_EMMCCLK_ID}, |
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{"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1}, |
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{"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1}, |
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{"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1}, |
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{"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1}, |
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{"aclk", M10V_PLL1DIV2, CLKSEL(9), 20, 4, aclk_table, 0, M10V_ACLK_ID}, |
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{"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1}, |
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{"hclk", M10V_PLL1DIV2, CLKSEL(9), 7, 5, hclk_table, 0, M10V_HCLK_ID}, |
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{"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1}, |
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{"pclk", M10V_PLL1DIV2, CLKSEL(9), 0, 7, pclk_table, 0, M10V_PCLK_ID}, |
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{"uhs1clk0", M10V_PLL7, CLKSEL(1), 3, 5, uhs1clk0_table, 0, -1}, |
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{"uhs2clk", M10V_PLL6DIV3, CLKSEL(1), 18, 4, uhs2clk_table, 0, -1}, |
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}; |
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static const struct m10v_clk_mux_factors m10v_mux_factor_data[] = { |
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{"spi", spi_mux_names, ARRAY_SIZE(spi_mux_names), |
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CLKSEL(8), 3, 7, spi_mux_table, 0, M10V_SPICLK_ID}, |
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{"uhs1clk2", uhs1clk2_mux_names, ARRAY_SIZE(uhs1clk2_mux_names), |
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CLKSEL(1), 13, 31, uhs1clk2_mux_table, 0, M10V_UHS1CLK2_ID}, |
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{"uhs1clk1", uhs1clk1_mux_names, ARRAY_SIZE(uhs1clk1_mux_names), |
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CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1}, |
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{"nfclk", nfclk_mux_names, ARRAY_SIZE(nfclk_mux_names), |
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CLKSEL(1), 22, 127, nfclk_mux_table, 0, M10V_NFCLK_ID}, |
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}; |
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static u8 m10v_mux_get_parent(struct clk_hw *hw) |
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{ |
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struct clk_mux *mux = to_clk_mux(hw); |
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u32 val; |
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val = readl(mux->reg) >> mux->shift; |
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val &= mux->mask; |
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return clk_mux_val_to_index(hw, mux->table, mux->flags, val); |
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} |
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static int m10v_mux_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct clk_mux *mux = to_clk_mux(hw); |
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u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); |
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unsigned long flags = 0; |
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u32 reg; |
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u32 write_en = BIT(fls(mux->mask) - 1); |
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if (mux->lock) |
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spin_lock_irqsave(mux->lock, flags); |
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else |
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__acquire(mux->lock); |
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reg = readl(mux->reg); |
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reg &= ~(mux->mask << mux->shift); |
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val = (val | write_en) << mux->shift; |
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reg |= val; |
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writel(reg, mux->reg); |
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if (mux->lock) |
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spin_unlock_irqrestore(mux->lock, flags); |
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else |
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__release(mux->lock); |
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return 0; |
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} |
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static const struct clk_ops m10v_mux_ops = { |
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.get_parent = m10v_mux_get_parent, |
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.set_parent = m10v_mux_set_parent, |
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.determine_rate = __clk_mux_determine_rate, |
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}; |
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static struct clk_hw *m10v_clk_hw_register_mux(struct device *dev, |
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const char *name, const char * const *parent_names, |
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u8 num_parents, unsigned long flags, void __iomem *reg, |
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u8 shift, u32 mask, u8 clk_mux_flags, u32 *table, |
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spinlock_t *lock) |
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{ |
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struct clk_mux *mux; |
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struct clk_hw *hw; |
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struct clk_init_data init; |
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int ret; |
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mux = kzalloc(sizeof(*mux), GFP_KERNEL); |
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if (!mux) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &m10v_mux_ops; |
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init.flags = flags; |
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init.parent_names = parent_names; |
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init.num_parents = num_parents; |
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mux->reg = reg; |
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mux->shift = shift; |
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mux->mask = mask; |
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mux->flags = clk_mux_flags; |
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mux->lock = lock; |
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mux->table = table; |
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mux->hw.init = &init; |
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hw = &mux->hw; |
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ret = clk_hw_register(dev, hw); |
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if (ret) { |
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kfree(mux); |
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hw = ERR_PTR(ret); |
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} |
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return hw; |
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} |
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struct m10v_clk_divider { |
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struct clk_hw hw; |
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void __iomem *reg; |
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u8 shift; |
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u8 width; |
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u8 flags; |
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const struct clk_div_table *table; |
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spinlock_t *lock; |
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void __iomem *write_valid_reg; |
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}; |
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static unsigned long m10v_clk_divider_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct m10v_clk_divider *divider = to_m10v_div(hw); |
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unsigned int val; |
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val = readl(divider->reg) >> divider->shift; |
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val &= clk_div_mask(divider->width); |
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return divider_recalc_rate(hw, parent_rate, val, divider->table, |
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divider->flags, divider->width); |
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} |
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static long m10v_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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struct m10v_clk_divider *divider = to_m10v_div(hw); |
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/* if read only, just return current value */ |
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if (divider->flags & CLK_DIVIDER_READ_ONLY) { |
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u32 val; |
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val = readl(divider->reg) >> divider->shift; |
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val &= clk_div_mask(divider->width); |
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return divider_ro_round_rate(hw, rate, prate, divider->table, |
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divider->width, divider->flags, |
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val); |
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} |
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return divider_round_rate(hw, rate, prate, divider->table, |
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divider->width, divider->flags); |
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} |
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static int m10v_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct m10v_clk_divider *divider = to_m10v_div(hw); |
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int value; |
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unsigned long flags = 0; |
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u32 val; |
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u32 write_en = BIT(divider->width - 1); |
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value = divider_get_val(rate, parent_rate, divider->table, |
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divider->width, divider->flags); |
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if (value < 0) |
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return value; |
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if (divider->lock) |
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spin_lock_irqsave(divider->lock, flags); |
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else |
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__acquire(divider->lock); |
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val = readl(divider->reg); |
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val &= ~(clk_div_mask(divider->width) << divider->shift); |
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val |= ((u32)value | write_en) << divider->shift; |
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writel(val, divider->reg); |
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if (divider->write_valid_reg) { |
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writel(M10V_DCHREQ, divider->write_valid_reg); |
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if (readl_poll_timeout(divider->write_valid_reg, val, |
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!val, M10V_UPOLL_RATE, M10V_UTIMEOUT)) |
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pr_err("%s:%s couldn't stabilize\n", |
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__func__, clk_hw_get_name(hw)); |
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} |
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if (divider->lock) |
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spin_unlock_irqrestore(divider->lock, flags); |
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else |
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__release(divider->lock); |
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return 0; |
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} |
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static const struct clk_ops m10v_clk_divider_ops = { |
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.recalc_rate = m10v_clk_divider_recalc_rate, |
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.round_rate = m10v_clk_divider_round_rate, |
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.set_rate = m10v_clk_divider_set_rate, |
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}; |
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static struct clk_hw *m10v_clk_hw_register_divider(struct device *dev, |
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const char *name, const char *parent_name, unsigned long flags, |
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void __iomem *reg, u8 shift, u8 width, |
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u8 clk_divider_flags, const struct clk_div_table *table, |
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spinlock_t *lock, void __iomem *write_valid_reg) |
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{ |
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struct m10v_clk_divider *div; |
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struct clk_hw *hw; |
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struct clk_init_data init; |
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int ret; |
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div = kzalloc(sizeof(*div), GFP_KERNEL); |
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if (!div) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &m10v_clk_divider_ops; |
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init.flags = flags; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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div->reg = reg; |
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div->shift = shift; |
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div->width = width; |
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div->flags = clk_divider_flags; |
|
div->lock = lock; |
|
div->hw.init = &init; |
|
div->table = table; |
|
div->write_valid_reg = write_valid_reg; |
|
|
|
/* register the clock */ |
|
hw = &div->hw; |
|
ret = clk_hw_register(dev, hw); |
|
if (ret) { |
|
kfree(div); |
|
hw = ERR_PTR(ret); |
|
} |
|
|
|
return hw; |
|
} |
|
|
|
static void m10v_reg_div_pre(const struct m10v_clk_div_factors *factors, |
|
struct clk_hw_onecell_data *clk_data, |
|
void __iomem *base) |
|
{ |
|
struct clk_hw *hw; |
|
void __iomem *write_valid_reg; |
|
|
|
/* |
|
* The registers on CLKSEL(9) or CLKSEL(10) need additional |
|
* writing to become valid. |
|
*/ |
|
if ((factors->offset == CLKSEL(9)) || (factors->offset == CLKSEL(10))) |
|
write_valid_reg = base + CLKSEL(11); |
|
else |
|
write_valid_reg = NULL; |
|
|
|
hw = m10v_clk_hw_register_divider(NULL, factors->name, |
|
factors->parent_name, |
|
CLK_SET_RATE_PARENT, |
|
base + factors->offset, |
|
factors->shift, |
|
factors->width, factors->div_flags, |
|
factors->table, |
|
&m10v_crglock, write_valid_reg); |
|
|
|
if (factors->onecell_idx >= 0) |
|
clk_data->hws[factors->onecell_idx] = hw; |
|
} |
|
|
|
static void m10v_reg_fixed_pre(const struct m10v_clk_div_fixed_data *factors, |
|
struct clk_hw_onecell_data *clk_data, |
|
const char *parent_name) |
|
{ |
|
struct clk_hw *hw; |
|
const char *pn = factors->parent_name ? |
|
factors->parent_name : parent_name; |
|
|
|
hw = clk_hw_register_fixed_factor(NULL, factors->name, pn, 0, |
|
factors->mult, factors->div); |
|
|
|
if (factors->onecell_idx >= 0) |
|
clk_data->hws[factors->onecell_idx] = hw; |
|
} |
|
|
|
static void m10v_reg_mux_pre(const struct m10v_clk_mux_factors *factors, |
|
struct clk_hw_onecell_data *clk_data, |
|
void __iomem *base) |
|
{ |
|
struct clk_hw *hw; |
|
|
|
hw = m10v_clk_hw_register_mux(NULL, factors->name, |
|
factors->parent_names, |
|
factors->num_parents, |
|
CLK_SET_RATE_PARENT, |
|
base + factors->offset, factors->shift, |
|
factors->mask, factors->mux_flags, |
|
factors->table, &m10v_crglock); |
|
|
|
if (factors->onecell_idx >= 0) |
|
clk_data->hws[factors->onecell_idx] = hw; |
|
} |
|
|
|
static int m10v_clk_probe(struct platform_device *pdev) |
|
{ |
|
int id; |
|
struct resource *res; |
|
struct device *dev = &pdev->dev; |
|
struct device_node *np = dev->of_node; |
|
void __iomem *base; |
|
const char *parent_name; |
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
|
base = devm_ioremap_resource(dev, res); |
|
if (IS_ERR(base)) |
|
return PTR_ERR(base); |
|
|
|
parent_name = of_clk_get_parent_name(np, 0); |
|
|
|
for (id = 0; id < ARRAY_SIZE(m10v_div_factor_data); ++id) |
|
m10v_reg_div_pre(&m10v_div_factor_data[id], |
|
m10v_clk_data, base); |
|
|
|
for (id = 0; id < ARRAY_SIZE(m10v_div_fixed_data); ++id) |
|
m10v_reg_fixed_pre(&m10v_div_fixed_data[id], |
|
m10v_clk_data, parent_name); |
|
|
|
for (id = 0; id < ARRAY_SIZE(m10v_mux_factor_data); ++id) |
|
m10v_reg_mux_pre(&m10v_mux_factor_data[id], |
|
m10v_clk_data, base); |
|
|
|
for (id = 0; id < M10V_NUM_CLKS; id++) { |
|
if (IS_ERR(m10v_clk_data->hws[id])) |
|
return PTR_ERR(m10v_clk_data->hws[id]); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
static const struct of_device_id m10v_clk_dt_ids[] = { |
|
{ .compatible = "socionext,milbeaut-m10v-ccu", }, |
|
{ } |
|
}; |
|
|
|
static struct platform_driver m10v_clk_driver = { |
|
.probe = m10v_clk_probe, |
|
.driver = { |
|
.name = "m10v-ccu", |
|
.of_match_table = m10v_clk_dt_ids, |
|
}, |
|
}; |
|
builtin_platform_driver(m10v_clk_driver); |
|
|
|
static void __init m10v_cc_init(struct device_node *np) |
|
{ |
|
int id; |
|
void __iomem *base; |
|
const char *parent_name; |
|
struct clk_hw *hw; |
|
|
|
m10v_clk_data = kzalloc(struct_size(m10v_clk_data, hws, |
|
M10V_NUM_CLKS), |
|
GFP_KERNEL); |
|
|
|
if (!m10v_clk_data) |
|
return; |
|
|
|
base = of_iomap(np, 0); |
|
if (!base) { |
|
kfree(m10v_clk_data); |
|
return; |
|
} |
|
|
|
parent_name = of_clk_get_parent_name(np, 0); |
|
if (!parent_name) { |
|
kfree(m10v_clk_data); |
|
iounmap(base); |
|
return; |
|
} |
|
|
|
/* |
|
* This way all clocks fetched before the platform device probes, |
|
* except those we assign here for early use, will be deferred. |
|
*/ |
|
for (id = 0; id < M10V_NUM_CLKS; id++) |
|
m10v_clk_data->hws[id] = ERR_PTR(-EPROBE_DEFER); |
|
|
|
/* |
|
* PLLs are set by bootloader so this driver registers them as the |
|
* fixed factor. |
|
*/ |
|
for (id = 0; id < ARRAY_SIZE(m10v_pll_fixed_data); ++id) |
|
m10v_reg_fixed_pre(&m10v_pll_fixed_data[id], |
|
m10v_clk_data, parent_name); |
|
|
|
/* |
|
* timer consumes "rclk" so it needs to register here. |
|
*/ |
|
hw = m10v_clk_hw_register_divider(NULL, "rclk", M10V_PLL10DIV2, 0, |
|
base + CLKSEL(1), 0, 3, 0, rclk_table, |
|
&m10v_crglock, NULL); |
|
m10v_clk_data->hws[M10V_RCLK_ID] = hw; |
|
|
|
m10v_clk_data->num = M10V_NUM_CLKS; |
|
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, m10v_clk_data); |
|
} |
|
CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init);
|
|
|