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463 lines
12 KiB
463 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Cortina Gemini SoC Clock Controller driver |
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* Copyright (c) 2017 Linus Walleij <[email protected]> |
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*/ |
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#define pr_fmt(fmt) "clk-gemini: " fmt |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/slab.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/clk-provider.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/mfd/syscon.h> |
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#include <linux/regmap.h> |
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#include <linux/spinlock.h> |
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#include <linux/reset-controller.h> |
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#include <dt-bindings/reset/cortina,gemini-reset.h> |
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#include <dt-bindings/clock/cortina,gemini-clock.h> |
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/* Globally visible clocks */ |
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static DEFINE_SPINLOCK(gemini_clk_lock); |
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#define GEMINI_GLOBAL_STATUS 0x04 |
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#define PLL_OSC_SEL BIT(30) |
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#define AHBSPEED_SHIFT (15) |
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#define AHBSPEED_MASK 0x07 |
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#define CPU_AHB_RATIO_SHIFT (18) |
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#define CPU_AHB_RATIO_MASK 0x03 |
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#define GEMINI_GLOBAL_PLL_CONTROL 0x08 |
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#define GEMINI_GLOBAL_SOFT_RESET 0x0c |
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#define GEMINI_GLOBAL_MISC_CONTROL 0x30 |
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#define PCI_CLK_66MHZ BIT(18) |
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#define GEMINI_GLOBAL_CLOCK_CONTROL 0x34 |
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#define PCI_CLKRUN_EN BIT(16) |
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#define TVC_HALFDIV_SHIFT (24) |
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#define TVC_HALFDIV_MASK 0x1f |
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#define SECURITY_CLK_SEL BIT(29) |
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#define GEMINI_GLOBAL_PCI_DLL_CONTROL 0x44 |
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#define PCI_DLL_BYPASS BIT(31) |
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#define PCI_DLL_TAP_SEL_MASK 0x1f |
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/** |
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* struct gemini_data_data - Gemini gated clocks |
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* @bit_idx: the bit used to gate this clock in the clock register |
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* @name: the clock name |
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* @parent_name: the name of the parent clock |
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* @flags: standard clock framework flags |
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*/ |
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struct gemini_gate_data { |
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u8 bit_idx; |
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const char *name; |
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const char *parent_name; |
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unsigned long flags; |
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}; |
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/** |
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* struct clk_gemini_pci - Gemini PCI clock |
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* @hw: corresponding clock hardware entry |
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* @map: regmap to access the registers |
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* @rate: current rate |
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*/ |
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struct clk_gemini_pci { |
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struct clk_hw hw; |
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struct regmap *map; |
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unsigned long rate; |
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}; |
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/** |
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* struct gemini_reset - gemini reset controller |
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* @map: regmap to access the containing system controller |
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* @rcdev: reset controller device |
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*/ |
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struct gemini_reset { |
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struct regmap *map; |
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struct reset_controller_dev rcdev; |
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}; |
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/* Keeps track of all clocks */ |
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static struct clk_hw_onecell_data *gemini_clk_data; |
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static const struct gemini_gate_data gemini_gates[] = { |
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{ 1, "security-gate", "secdiv", 0 }, |
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{ 2, "gmac0-gate", "ahb", 0 }, |
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{ 3, "gmac1-gate", "ahb", 0 }, |
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{ 4, "sata0-gate", "ahb", 0 }, |
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{ 5, "sata1-gate", "ahb", 0 }, |
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{ 6, "usb0-gate", "ahb", 0 }, |
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{ 7, "usb1-gate", "ahb", 0 }, |
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{ 8, "ide-gate", "ahb", 0 }, |
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{ 9, "pci-gate", "ahb", 0 }, |
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/* |
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* The DDR controller may never have a driver, but certainly must |
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* not be gated off. |
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*/ |
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{ 10, "ddr-gate", "ahb", CLK_IS_CRITICAL }, |
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/* |
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* The flash controller must be on to access NOR flash through the |
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* memory map. |
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*/ |
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{ 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED }, |
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{ 12, "tvc-gate", "ahb", 0 }, |
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{ 13, "boot-gate", "apb", 0 }, |
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}; |
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#define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw) |
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#define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev) |
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static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct clk_gemini_pci *pciclk = to_pciclk(hw); |
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u32 val; |
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regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val); |
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if (val & PCI_CLK_66MHZ) |
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return 66000000; |
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return 33000000; |
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} |
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static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *prate) |
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{ |
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/* We support 33 and 66 MHz */ |
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if (rate < 48000000) |
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return 33000000; |
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return 66000000; |
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} |
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static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct clk_gemini_pci *pciclk = to_pciclk(hw); |
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if (rate == 33000000) |
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return regmap_update_bits(pciclk->map, |
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GEMINI_GLOBAL_MISC_CONTROL, |
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PCI_CLK_66MHZ, 0); |
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if (rate == 66000000) |
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return regmap_update_bits(pciclk->map, |
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GEMINI_GLOBAL_MISC_CONTROL, |
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0, PCI_CLK_66MHZ); |
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return -EINVAL; |
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} |
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static int gemini_pci_enable(struct clk_hw *hw) |
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{ |
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struct clk_gemini_pci *pciclk = to_pciclk(hw); |
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regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, |
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0, PCI_CLKRUN_EN); |
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return 0; |
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} |
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static void gemini_pci_disable(struct clk_hw *hw) |
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{ |
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struct clk_gemini_pci *pciclk = to_pciclk(hw); |
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regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, |
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PCI_CLKRUN_EN, 0); |
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} |
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static int gemini_pci_is_enabled(struct clk_hw *hw) |
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{ |
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struct clk_gemini_pci *pciclk = to_pciclk(hw); |
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unsigned int val; |
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regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val); |
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return !!(val & PCI_CLKRUN_EN); |
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} |
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static const struct clk_ops gemini_pci_clk_ops = { |
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.recalc_rate = gemini_pci_recalc_rate, |
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.round_rate = gemini_pci_round_rate, |
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.set_rate = gemini_pci_set_rate, |
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.enable = gemini_pci_enable, |
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.disable = gemini_pci_disable, |
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.is_enabled = gemini_pci_is_enabled, |
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}; |
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static struct clk_hw *gemini_pci_clk_setup(const char *name, |
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const char *parent_name, |
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struct regmap *map) |
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{ |
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struct clk_gemini_pci *pciclk; |
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struct clk_init_data init; |
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int ret; |
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pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL); |
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if (!pciclk) |
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return ERR_PTR(-ENOMEM); |
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init.name = name; |
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init.ops = &gemini_pci_clk_ops; |
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init.flags = 0; |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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pciclk->map = map; |
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pciclk->hw.init = &init; |
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ret = clk_hw_register(NULL, &pciclk->hw); |
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if (ret) { |
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kfree(pciclk); |
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return ERR_PTR(ret); |
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} |
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return &pciclk->hw; |
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} |
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/* |
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* This is a self-deasserting reset controller. |
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*/ |
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static int gemini_reset(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct gemini_reset *gr = to_gemini_reset(rcdev); |
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/* Manual says to always set BIT 30 (CPU1) to 1 */ |
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return regmap_write(gr->map, |
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GEMINI_GLOBAL_SOFT_RESET, |
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BIT(GEMINI_RESET_CPU1) | BIT(id)); |
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} |
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static int gemini_reset_assert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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return 0; |
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} |
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static int gemini_reset_deassert(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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return 0; |
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} |
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static int gemini_reset_status(struct reset_controller_dev *rcdev, |
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unsigned long id) |
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{ |
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struct gemini_reset *gr = to_gemini_reset(rcdev); |
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u32 val; |
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int ret; |
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ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val); |
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if (ret) |
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return ret; |
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return !!(val & BIT(id)); |
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} |
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static const struct reset_control_ops gemini_reset_ops = { |
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.reset = gemini_reset, |
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.assert = gemini_reset_assert, |
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.deassert = gemini_reset_deassert, |
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.status = gemini_reset_status, |
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}; |
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static int gemini_clk_probe(struct platform_device *pdev) |
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{ |
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/* Gives the fracions 1x, 1.5x, 1.85x and 2x */ |
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unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 }; |
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unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 }; |
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void __iomem *base; |
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struct gemini_reset *gr; |
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struct regmap *map; |
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struct clk_hw *hw; |
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struct device *dev = &pdev->dev; |
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struct device_node *np = dev->of_node; |
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unsigned int mult, div; |
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struct resource *res; |
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u32 val; |
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int ret; |
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int i; |
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gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL); |
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if (!gr) |
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return -ENOMEM; |
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/* Remap the system controller for the exclusive register */ |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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base = devm_ioremap_resource(dev, res); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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map = syscon_node_to_regmap(np); |
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if (IS_ERR(map)) { |
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dev_err(dev, "no syscon regmap\n"); |
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return PTR_ERR(map); |
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} |
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gr->map = map; |
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gr->rcdev.owner = THIS_MODULE; |
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gr->rcdev.nr_resets = 32; |
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gr->rcdev.ops = &gemini_reset_ops; |
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gr->rcdev.of_node = np; |
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ret = devm_reset_controller_register(dev, &gr->rcdev); |
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if (ret) { |
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dev_err(dev, "could not register reset controller\n"); |
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return ret; |
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} |
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/* RTC clock 32768 Hz */ |
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hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768); |
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gemini_clk_data->hws[GEMINI_CLK_RTC] = hw; |
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/* CPU clock derived as a fixed ratio from the AHB clock */ |
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regmap_read(map, GEMINI_GLOBAL_STATUS, &val); |
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val >>= CPU_AHB_RATIO_SHIFT; |
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val &= CPU_AHB_RATIO_MASK; |
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hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0, |
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cpu_ahb_mult[val], |
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cpu_ahb_div[val]); |
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gemini_clk_data->hws[GEMINI_CLK_CPU] = hw; |
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/* Security clock is 1:1 or 0.75 of APB */ |
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regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val); |
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if (val & SECURITY_CLK_SEL) { |
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mult = 1; |
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div = 1; |
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} else { |
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mult = 3; |
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div = 4; |
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} |
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hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div); |
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/* |
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* These are the leaf gates, at boot no clocks are gated. |
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*/ |
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for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) { |
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const struct gemini_gate_data *gd; |
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gd = &gemini_gates[i]; |
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gemini_clk_data->hws[GEMINI_CLK_GATES + i] = |
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clk_hw_register_gate(NULL, gd->name, |
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gd->parent_name, |
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gd->flags, |
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base + GEMINI_GLOBAL_CLOCK_CONTROL, |
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gd->bit_idx, |
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CLK_GATE_SET_TO_DISABLE, |
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&gemini_clk_lock); |
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} |
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/* |
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* The TV Interface Controller has a 5-bit half divider register. |
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* This clock is supposed to be 27MHz as this is an exact multiple |
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* of PAL and NTSC frequencies. The register is undocumented :( |
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* FIXME: figure out the parent and how the divider works. |
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*/ |
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mult = 1; |
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div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK); |
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dev_dbg(dev, "TVC half divider value = %d\n", div); |
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div += 1; |
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hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000); |
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gemini_clk_data->hws[GEMINI_CLK_TVC] = hw; |
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/* FIXME: very unclear what the parent is */ |
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hw = gemini_pci_clk_setup("PCI", "xtal", map); |
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gemini_clk_data->hws[GEMINI_CLK_PCI] = hw; |
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/* FIXME: very unclear what the parent is */ |
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hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000); |
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gemini_clk_data->hws[GEMINI_CLK_UART] = hw; |
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return 0; |
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} |
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static const struct of_device_id gemini_clk_dt_ids[] = { |
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{ .compatible = "cortina,gemini-syscon", }, |
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{ /* sentinel */ }, |
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}; |
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static struct platform_driver gemini_clk_driver = { |
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.probe = gemini_clk_probe, |
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.driver = { |
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.name = "gemini-clk", |
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.of_match_table = gemini_clk_dt_ids, |
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.suppress_bind_attrs = true, |
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}, |
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}; |
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builtin_platform_driver(gemini_clk_driver); |
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static void __init gemini_cc_init(struct device_node *np) |
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{ |
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struct regmap *map; |
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struct clk_hw *hw; |
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unsigned long freq; |
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unsigned int mult, div; |
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u32 val; |
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int ret; |
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int i; |
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gemini_clk_data = kzalloc(struct_size(gemini_clk_data, hws, |
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GEMINI_NUM_CLKS), |
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GFP_KERNEL); |
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if (!gemini_clk_data) |
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return; |
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/* |
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* This way all clock fetched before the platform device probes, |
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* except those we assign here for early use, will be deferred. |
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*/ |
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for (i = 0; i < GEMINI_NUM_CLKS; i++) |
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gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); |
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map = syscon_node_to_regmap(np); |
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if (IS_ERR(map)) { |
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pr_err("no syscon regmap\n"); |
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return; |
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} |
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/* |
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* We check that the regmap works on this very first access, |
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* but as this is an MMIO-backed regmap, subsequent regmap |
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* access is not going to fail and we skip error checks from |
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* this point. |
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*/ |
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ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val); |
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if (ret) { |
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pr_err("failed to read global status register\n"); |
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return; |
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} |
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/* |
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* XTAL is the crystal oscillator, 60 or 30 MHz selected from |
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* strap pin E6 |
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*/ |
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if (val & PLL_OSC_SEL) |
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freq = 30000000; |
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else |
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freq = 60000000; |
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hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq); |
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pr_debug("main crystal @%lu MHz\n", freq / 1000000); |
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/* VCO clock derived from the crystal */ |
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mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK); |
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div = 2; |
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/* If we run on 30 MHz crystal we have to multiply with two */ |
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if (val & PLL_OSC_SEL) |
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mult *= 2; |
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hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div); |
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/* The AHB clock is always 1/3 of the VCO */ |
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hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3); |
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gemini_clk_data->hws[GEMINI_CLK_AHB] = hw; |
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/* The APB clock is always 1/6 of the AHB */ |
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hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6); |
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gemini_clk_data->hws[GEMINI_CLK_APB] = hw; |
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/* Register the clocks to be accessed by the device tree */ |
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gemini_clk_data->num = GEMINI_NUM_CLKS; |
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data); |
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} |
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CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);
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