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703 lines
18 KiB
703 lines
18 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* TI CDCE706 programmable 3-PLL clock synthesizer driver |
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* |
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* Copyright (c) 2014 Cadence Design Systems Inc. |
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* |
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* Reference: https://www.ti.com/lit/ds/symlink/cdce706.pdf |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clk-provider.h> |
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#include <linux/delay.h> |
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#include <linux/i2c.h> |
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#include <linux/interrupt.h> |
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#include <linux/mod_devicetable.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/rational.h> |
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#include <linux/regmap.h> |
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#include <linux/slab.h> |
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#define CDCE706_CLKIN_CLOCK 10 |
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#define CDCE706_CLKIN_SOURCE 11 |
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#define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll)) |
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#define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll)) |
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#define CDCE706_PLL_HI(pll) (3 + 3 * (pll)) |
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#define CDCE706_PLL_MUX 3 |
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#define CDCE706_PLL_FVCO 6 |
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#define CDCE706_DIVIDER(div) (13 + (div)) |
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#define CDCE706_CLKOUT(out) (19 + (out)) |
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#define CDCE706_CLKIN_CLOCK_MASK 0x10 |
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#define CDCE706_CLKIN_SOURCE_SHIFT 6 |
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#define CDCE706_CLKIN_SOURCE_MASK 0xc0 |
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#define CDCE706_CLKIN_SOURCE_LVCMOS 0x40 |
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#define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll)) |
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#define CDCE706_PLL_LOW_M_MASK 0xff |
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#define CDCE706_PLL_LOW_N_MASK 0xff |
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#define CDCE706_PLL_HI_M_MASK 0x1 |
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#define CDCE706_PLL_HI_N_MASK 0x1e |
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#define CDCE706_PLL_HI_N_SHIFT 1 |
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#define CDCE706_PLL_M_MAX 0x1ff |
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#define CDCE706_PLL_N_MAX 0xfff |
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#define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll)) |
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#define CDCE706_PLL_FREQ_MIN 80000000 |
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#define CDCE706_PLL_FREQ_MAX 300000000 |
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#define CDCE706_PLL_FREQ_HI 180000000 |
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#define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4)) |
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#define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1)) |
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#define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div)) |
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#define CDCE706_DIVIDER_DIVIDER_MASK 0x7f |
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#define CDCE706_DIVIDER_DIVIDER_MAX 0x7f |
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#define CDCE706_CLKOUT_DIVIDER_MASK 0x7 |
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#define CDCE706_CLKOUT_ENABLE_MASK 0x8 |
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static const struct regmap_config cdce706_regmap_config = { |
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.reg_bits = 8, |
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.val_bits = 8, |
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.val_format_endian = REGMAP_ENDIAN_NATIVE, |
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}; |
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#define to_hw_data(phw) (container_of((phw), struct cdce706_hw_data, hw)) |
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struct cdce706_hw_data { |
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struct cdce706_dev_data *dev_data; |
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unsigned idx; |
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unsigned parent; |
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struct clk_hw hw; |
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unsigned div; |
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unsigned mul; |
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unsigned mux; |
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}; |
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struct cdce706_dev_data { |
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struct i2c_client *client; |
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struct regmap *regmap; |
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struct clk *clkin_clk[2]; |
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const char *clkin_name[2]; |
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struct cdce706_hw_data clkin[1]; |
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struct cdce706_hw_data pll[3]; |
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struct cdce706_hw_data divider[6]; |
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struct cdce706_hw_data clkout[6]; |
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}; |
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static const char * const cdce706_source_name[] = { |
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"clk_in0", "clk_in1", |
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}; |
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static const char * const cdce706_clkin_name[] = { |
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"clk_in", |
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}; |
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static const char * const cdce706_pll_name[] = { |
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"pll1", "pll2", "pll3", |
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}; |
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static const char * const cdce706_divider_parent_name[] = { |
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"clk_in", "pll1", "pll2", "pll2", "pll3", |
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}; |
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static const char *cdce706_divider_name[] = { |
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"p0", "p1", "p2", "p3", "p4", "p5", |
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}; |
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static const char * const cdce706_clkout_name[] = { |
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"clk_out0", "clk_out1", "clk_out2", "clk_out3", "clk_out4", "clk_out5", |
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}; |
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static int cdce706_reg_read(struct cdce706_dev_data *dev_data, unsigned reg, |
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unsigned *val) |
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{ |
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int rc = regmap_read(dev_data->regmap, reg | 0x80, val); |
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if (rc < 0) |
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dev_err(&dev_data->client->dev, "error reading reg %u", reg); |
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return rc; |
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} |
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static int cdce706_reg_write(struct cdce706_dev_data *dev_data, unsigned reg, |
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unsigned val) |
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{ |
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int rc = regmap_write(dev_data->regmap, reg | 0x80, val); |
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if (rc < 0) |
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dev_err(&dev_data->client->dev, "error writing reg %u", reg); |
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return rc; |
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} |
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static int cdce706_reg_update(struct cdce706_dev_data *dev_data, unsigned reg, |
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unsigned mask, unsigned val) |
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{ |
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int rc = regmap_update_bits(dev_data->regmap, reg | 0x80, mask, val); |
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if (rc < 0) |
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dev_err(&dev_data->client->dev, "error updating reg %u", reg); |
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return rc; |
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} |
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static int cdce706_clkin_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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hwd->parent = index; |
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return 0; |
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} |
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static u8 cdce706_clkin_get_parent(struct clk_hw *hw) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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return hwd->parent; |
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} |
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static const struct clk_ops cdce706_clkin_ops = { |
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.set_parent = cdce706_clkin_set_parent, |
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.get_parent = cdce706_clkin_get_parent, |
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}; |
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static unsigned long cdce706_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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dev_dbg(&hwd->dev_data->client->dev, |
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"%s, pll: %d, mux: %d, mul: %u, div: %u\n", |
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__func__, hwd->idx, hwd->mux, hwd->mul, hwd->div); |
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if (!hwd->mux) { |
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if (hwd->div && hwd->mul) { |
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u64 res = (u64)parent_rate * hwd->mul; |
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do_div(res, hwd->div); |
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return res; |
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} |
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} else { |
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if (hwd->div) |
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return parent_rate / hwd->div; |
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} |
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return 0; |
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} |
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static long cdce706_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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unsigned long mul, div; |
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u64 res; |
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dev_dbg(&hwd->dev_data->client->dev, |
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"%s, rate: %lu, parent_rate: %lu\n", |
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__func__, rate, *parent_rate); |
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rational_best_approximation(rate, *parent_rate, |
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CDCE706_PLL_N_MAX, CDCE706_PLL_M_MAX, |
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&mul, &div); |
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hwd->mul = mul; |
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hwd->div = div; |
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dev_dbg(&hwd->dev_data->client->dev, |
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"%s, pll: %d, mul: %lu, div: %lu\n", |
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__func__, hwd->idx, mul, div); |
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res = (u64)*parent_rate * hwd->mul; |
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do_div(res, hwd->div); |
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return res; |
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} |
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static int cdce706_pll_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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unsigned long mul = hwd->mul, div = hwd->div; |
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int err; |
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dev_dbg(&hwd->dev_data->client->dev, |
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"%s, pll: %d, mul: %lu, div: %lu\n", |
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__func__, hwd->idx, mul, div); |
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err = cdce706_reg_update(hwd->dev_data, |
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CDCE706_PLL_HI(hwd->idx), |
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CDCE706_PLL_HI_M_MASK | CDCE706_PLL_HI_N_MASK, |
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((div >> 8) & CDCE706_PLL_HI_M_MASK) | |
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((mul >> (8 - CDCE706_PLL_HI_N_SHIFT)) & |
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CDCE706_PLL_HI_N_MASK)); |
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if (err < 0) |
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return err; |
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err = cdce706_reg_write(hwd->dev_data, |
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CDCE706_PLL_M_LOW(hwd->idx), |
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div & CDCE706_PLL_LOW_M_MASK); |
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if (err < 0) |
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return err; |
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err = cdce706_reg_write(hwd->dev_data, |
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CDCE706_PLL_N_LOW(hwd->idx), |
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mul & CDCE706_PLL_LOW_N_MASK); |
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if (err < 0) |
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return err; |
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err = cdce706_reg_update(hwd->dev_data, |
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CDCE706_PLL_FVCO, |
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CDCE706_PLL_FVCO_MASK(hwd->idx), |
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rate > CDCE706_PLL_FREQ_HI ? |
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CDCE706_PLL_FVCO_MASK(hwd->idx) : 0); |
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return err; |
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} |
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static const struct clk_ops cdce706_pll_ops = { |
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.recalc_rate = cdce706_pll_recalc_rate, |
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.round_rate = cdce706_pll_round_rate, |
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.set_rate = cdce706_pll_set_rate, |
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}; |
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static int cdce706_divider_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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if (hwd->parent == index) |
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return 0; |
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hwd->parent = index; |
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return cdce706_reg_update(hwd->dev_data, |
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CDCE706_DIVIDER_PLL(hwd->idx), |
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CDCE706_DIVIDER_PLL_MASK(hwd->idx), |
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index << CDCE706_DIVIDER_PLL_SHIFT(hwd->idx)); |
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} |
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static u8 cdce706_divider_get_parent(struct clk_hw *hw) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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return hwd->parent; |
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} |
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static unsigned long cdce706_divider_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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dev_dbg(&hwd->dev_data->client->dev, |
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"%s, divider: %d, div: %u\n", |
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__func__, hwd->idx, hwd->div); |
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if (hwd->div) |
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return parent_rate / hwd->div; |
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return 0; |
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} |
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static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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struct cdce706_dev_data *cdce = hwd->dev_data; |
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unsigned long mul, div; |
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dev_dbg(&hwd->dev_data->client->dev, |
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"%s, rate: %lu, parent_rate: %lu\n", |
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__func__, rate, *parent_rate); |
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rational_best_approximation(rate, *parent_rate, |
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1, CDCE706_DIVIDER_DIVIDER_MAX, |
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&mul, &div); |
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if (!mul) |
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div = CDCE706_DIVIDER_DIVIDER_MAX; |
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if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { |
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unsigned long best_diff = rate; |
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unsigned long best_div = 0; |
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struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent]; |
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unsigned long gp_rate = gp_clk ? clk_get_rate(gp_clk) : 0; |
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for (div = CDCE706_PLL_FREQ_MIN / rate; best_diff && |
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div <= CDCE706_PLL_FREQ_MAX / rate; ++div) { |
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unsigned long n, m; |
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unsigned long diff; |
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unsigned long div_rate; |
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u64 div_rate64; |
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if (rate * div < CDCE706_PLL_FREQ_MIN) |
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continue; |
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rational_best_approximation(rate * div, gp_rate, |
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CDCE706_PLL_N_MAX, |
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CDCE706_PLL_M_MAX, |
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&n, &m); |
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div_rate64 = (u64)gp_rate * n; |
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do_div(div_rate64, m); |
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do_div(div_rate64, div); |
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div_rate = div_rate64; |
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diff = max(div_rate, rate) - min(div_rate, rate); |
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if (diff < best_diff) { |
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best_diff = diff; |
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best_div = div; |
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dev_dbg(&hwd->dev_data->client->dev, |
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"%s, %lu * %lu / %lu / %lu = %lu\n", |
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__func__, gp_rate, n, m, div, div_rate); |
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} |
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} |
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div = best_div; |
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dev_dbg(&hwd->dev_data->client->dev, |
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"%s, altering parent rate: %lu -> %lu\n", |
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__func__, *parent_rate, rate * div); |
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*parent_rate = rate * div; |
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} |
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hwd->div = div; |
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dev_dbg(&hwd->dev_data->client->dev, |
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"%s, divider: %d, div: %lu\n", |
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__func__, hwd->idx, div); |
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return *parent_rate / div; |
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} |
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static int cdce706_divider_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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dev_dbg(&hwd->dev_data->client->dev, |
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"%s, divider: %d, div: %u\n", |
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__func__, hwd->idx, hwd->div); |
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return cdce706_reg_update(hwd->dev_data, |
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CDCE706_DIVIDER(hwd->idx), |
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CDCE706_DIVIDER_DIVIDER_MASK, |
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hwd->div); |
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} |
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static const struct clk_ops cdce706_divider_ops = { |
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.set_parent = cdce706_divider_set_parent, |
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.get_parent = cdce706_divider_get_parent, |
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.recalc_rate = cdce706_divider_recalc_rate, |
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.round_rate = cdce706_divider_round_rate, |
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.set_rate = cdce706_divider_set_rate, |
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}; |
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static int cdce706_clkout_prepare(struct clk_hw *hw) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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return cdce706_reg_update(hwd->dev_data, CDCE706_CLKOUT(hwd->idx), |
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CDCE706_CLKOUT_ENABLE_MASK, |
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CDCE706_CLKOUT_ENABLE_MASK); |
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} |
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static void cdce706_clkout_unprepare(struct clk_hw *hw) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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cdce706_reg_update(hwd->dev_data, CDCE706_CLKOUT(hwd->idx), |
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CDCE706_CLKOUT_ENABLE_MASK, 0); |
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} |
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static int cdce706_clkout_set_parent(struct clk_hw *hw, u8 index) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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if (hwd->parent == index) |
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return 0; |
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hwd->parent = index; |
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return cdce706_reg_update(hwd->dev_data, |
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CDCE706_CLKOUT(hwd->idx), |
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CDCE706_CLKOUT_ENABLE_MASK, index); |
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} |
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static u8 cdce706_clkout_get_parent(struct clk_hw *hw) |
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{ |
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struct cdce706_hw_data *hwd = to_hw_data(hw); |
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return hwd->parent; |
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} |
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static unsigned long cdce706_clkout_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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return parent_rate; |
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} |
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static long cdce706_clkout_round_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long *parent_rate) |
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{ |
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*parent_rate = rate; |
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return rate; |
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} |
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static int cdce706_clkout_set_rate(struct clk_hw *hw, unsigned long rate, |
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unsigned long parent_rate) |
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{ |
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return 0; |
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} |
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static const struct clk_ops cdce706_clkout_ops = { |
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.prepare = cdce706_clkout_prepare, |
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.unprepare = cdce706_clkout_unprepare, |
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.set_parent = cdce706_clkout_set_parent, |
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.get_parent = cdce706_clkout_get_parent, |
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.recalc_rate = cdce706_clkout_recalc_rate, |
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.round_rate = cdce706_clkout_round_rate, |
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.set_rate = cdce706_clkout_set_rate, |
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}; |
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static int cdce706_register_hw(struct cdce706_dev_data *cdce, |
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struct cdce706_hw_data *hw, unsigned num_hw, |
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const char * const *clk_names, |
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struct clk_init_data *init) |
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{ |
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unsigned i; |
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int ret; |
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for (i = 0; i < num_hw; ++i, ++hw) { |
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init->name = clk_names[i]; |
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hw->dev_data = cdce; |
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hw->idx = i; |
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hw->hw.init = init; |
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ret = devm_clk_hw_register(&cdce->client->dev, |
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&hw->hw); |
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if (ret) { |
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dev_err(&cdce->client->dev, "Failed to register %s\n", |
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clk_names[i]); |
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return ret; |
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} |
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} |
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return 0; |
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} |
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static int cdce706_register_clkin(struct cdce706_dev_data *cdce) |
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{ |
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struct clk_init_data init = { |
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.ops = &cdce706_clkin_ops, |
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.parent_names = cdce->clkin_name, |
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.num_parents = ARRAY_SIZE(cdce->clkin_name), |
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}; |
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unsigned i; |
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int ret; |
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unsigned clock, source; |
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for (i = 0; i < ARRAY_SIZE(cdce->clkin_name); ++i) { |
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struct clk *parent = devm_clk_get(&cdce->client->dev, |
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cdce706_source_name[i]); |
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if (IS_ERR(parent)) { |
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cdce->clkin_name[i] = cdce706_source_name[i]; |
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} else { |
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cdce->clkin_name[i] = __clk_get_name(parent); |
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cdce->clkin_clk[i] = parent; |
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} |
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} |
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ret = cdce706_reg_read(cdce, CDCE706_CLKIN_SOURCE, &source); |
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if (ret < 0) |
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return ret; |
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if ((source & CDCE706_CLKIN_SOURCE_MASK) == |
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CDCE706_CLKIN_SOURCE_LVCMOS) { |
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ret = cdce706_reg_read(cdce, CDCE706_CLKIN_CLOCK, &clock); |
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if (ret < 0) |
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return ret; |
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cdce->clkin[0].parent = !!(clock & CDCE706_CLKIN_CLOCK_MASK); |
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} |
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ret = cdce706_register_hw(cdce, cdce->clkin, |
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ARRAY_SIZE(cdce->clkin), |
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cdce706_clkin_name, &init); |
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return ret; |
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} |
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static int cdce706_register_plls(struct cdce706_dev_data *cdce) |
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{ |
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struct clk_init_data init = { |
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.ops = &cdce706_pll_ops, |
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.parent_names = cdce706_clkin_name, |
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.num_parents = ARRAY_SIZE(cdce706_clkin_name), |
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}; |
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unsigned i; |
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int ret; |
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unsigned mux; |
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ret = cdce706_reg_read(cdce, CDCE706_PLL_MUX, &mux); |
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if (ret < 0) |
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return ret; |
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for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) { |
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unsigned m, n, v; |
|
|
|
ret = cdce706_reg_read(cdce, CDCE706_PLL_M_LOW(i), &m); |
|
if (ret < 0) |
|
return ret; |
|
ret = cdce706_reg_read(cdce, CDCE706_PLL_N_LOW(i), &n); |
|
if (ret < 0) |
|
return ret; |
|
ret = cdce706_reg_read(cdce, CDCE706_PLL_HI(i), &v); |
|
if (ret < 0) |
|
return ret; |
|
cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8); |
|
cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) << |
|
(8 - CDCE706_PLL_HI_N_SHIFT)); |
|
cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i); |
|
dev_dbg(&cdce->client->dev, |
|
"%s: i: %u, div: %u, mul: %u, mux: %d\n", __func__, i, |
|
cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux); |
|
} |
|
|
|
ret = cdce706_register_hw(cdce, cdce->pll, |
|
ARRAY_SIZE(cdce->pll), |
|
cdce706_pll_name, &init); |
|
return ret; |
|
} |
|
|
|
static int cdce706_register_dividers(struct cdce706_dev_data *cdce) |
|
{ |
|
struct clk_init_data init = { |
|
.ops = &cdce706_divider_ops, |
|
.parent_names = cdce706_divider_parent_name, |
|
.num_parents = ARRAY_SIZE(cdce706_divider_parent_name), |
|
.flags = CLK_SET_RATE_PARENT, |
|
}; |
|
unsigned i; |
|
int ret; |
|
|
|
for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) { |
|
unsigned val; |
|
|
|
ret = cdce706_reg_read(cdce, CDCE706_DIVIDER_PLL(i), &val); |
|
if (ret < 0) |
|
return ret; |
|
cdce->divider[i].parent = |
|
(val & CDCE706_DIVIDER_PLL_MASK(i)) >> |
|
CDCE706_DIVIDER_PLL_SHIFT(i); |
|
|
|
ret = cdce706_reg_read(cdce, CDCE706_DIVIDER(i), &val); |
|
if (ret < 0) |
|
return ret; |
|
cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK; |
|
dev_dbg(&cdce->client->dev, |
|
"%s: i: %u, parent: %u, div: %u\n", __func__, i, |
|
cdce->divider[i].parent, cdce->divider[i].div); |
|
} |
|
|
|
ret = cdce706_register_hw(cdce, cdce->divider, |
|
ARRAY_SIZE(cdce->divider), |
|
cdce706_divider_name, &init); |
|
return ret; |
|
} |
|
|
|
static int cdce706_register_clkouts(struct cdce706_dev_data *cdce) |
|
{ |
|
struct clk_init_data init = { |
|
.ops = &cdce706_clkout_ops, |
|
.parent_names = cdce706_divider_name, |
|
.num_parents = ARRAY_SIZE(cdce706_divider_name), |
|
.flags = CLK_SET_RATE_PARENT, |
|
}; |
|
unsigned i; |
|
int ret; |
|
|
|
for (i = 0; i < ARRAY_SIZE(cdce->clkout); ++i) { |
|
unsigned val; |
|
|
|
ret = cdce706_reg_read(cdce, CDCE706_CLKOUT(i), &val); |
|
if (ret < 0) |
|
return ret; |
|
cdce->clkout[i].parent = val & CDCE706_CLKOUT_DIVIDER_MASK; |
|
dev_dbg(&cdce->client->dev, |
|
"%s: i: %u, parent: %u\n", __func__, i, |
|
cdce->clkout[i].parent); |
|
} |
|
|
|
return cdce706_register_hw(cdce, cdce->clkout, |
|
ARRAY_SIZE(cdce->clkout), |
|
cdce706_clkout_name, &init); |
|
} |
|
|
|
static struct clk_hw * |
|
of_clk_cdce_get(struct of_phandle_args *clkspec, void *data) |
|
{ |
|
struct cdce706_dev_data *cdce = data; |
|
unsigned int idx = clkspec->args[0]; |
|
|
|
if (idx >= ARRAY_SIZE(cdce->clkout)) { |
|
pr_err("%s: invalid index %u\n", __func__, idx); |
|
return ERR_PTR(-EINVAL); |
|
} |
|
|
|
return &cdce->clkout[idx].hw; |
|
} |
|
|
|
static int cdce706_probe(struct i2c_client *client, |
|
const struct i2c_device_id *id) |
|
{ |
|
struct i2c_adapter *adapter = client->adapter; |
|
struct cdce706_dev_data *cdce; |
|
int ret; |
|
|
|
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) |
|
return -EIO; |
|
|
|
cdce = devm_kzalloc(&client->dev, sizeof(*cdce), GFP_KERNEL); |
|
if (!cdce) |
|
return -ENOMEM; |
|
|
|
cdce->client = client; |
|
cdce->regmap = devm_regmap_init_i2c(client, &cdce706_regmap_config); |
|
if (IS_ERR(cdce->regmap)) { |
|
dev_err(&client->dev, "Failed to initialize regmap\n"); |
|
return -EINVAL; |
|
} |
|
|
|
i2c_set_clientdata(client, cdce); |
|
|
|
ret = cdce706_register_clkin(cdce); |
|
if (ret < 0) |
|
return ret; |
|
ret = cdce706_register_plls(cdce); |
|
if (ret < 0) |
|
return ret; |
|
ret = cdce706_register_dividers(cdce); |
|
if (ret < 0) |
|
return ret; |
|
ret = cdce706_register_clkouts(cdce); |
|
if (ret < 0) |
|
return ret; |
|
return of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce_get, |
|
cdce); |
|
} |
|
|
|
static int cdce706_remove(struct i2c_client *client) |
|
{ |
|
of_clk_del_provider(client->dev.of_node); |
|
return 0; |
|
} |
|
|
|
|
|
#ifdef CONFIG_OF |
|
static const struct of_device_id cdce706_dt_match[] = { |
|
{ .compatible = "ti,cdce706" }, |
|
{ }, |
|
}; |
|
MODULE_DEVICE_TABLE(of, cdce706_dt_match); |
|
#endif |
|
|
|
static const struct i2c_device_id cdce706_id[] = { |
|
{ "cdce706", 0 }, |
|
{ } |
|
}; |
|
MODULE_DEVICE_TABLE(i2c, cdce706_id); |
|
|
|
static struct i2c_driver cdce706_i2c_driver = { |
|
.driver = { |
|
.name = "cdce706", |
|
.of_match_table = of_match_ptr(cdce706_dt_match), |
|
}, |
|
.probe = cdce706_probe, |
|
.remove = cdce706_remove, |
|
.id_table = cdce706_id, |
|
}; |
|
module_i2c_driver(cdce706_i2c_driver); |
|
|
|
MODULE_AUTHOR("Max Filippov <[email protected]>"); |
|
MODULE_DESCRIPTION("TI CDCE 706 clock synthesizer driver"); |
|
MODULE_LICENSE("GPL");
|
|
|