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341 lines
11 KiB
341 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* Copyright (c) 2014 Oleksij Rempel <[email protected]>. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/clkdev.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/clk-provider.h> |
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#include <linux/spinlock.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <dt-bindings/clock/alphascale,asm9260.h> |
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#define HW_AHBCLKCTRL0 0x0020 |
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#define HW_AHBCLKCTRL1 0x0030 |
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#define HW_SYSPLLCTRL 0x0100 |
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#define HW_MAINCLKSEL 0x0120 |
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#define HW_MAINCLKUEN 0x0124 |
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#define HW_UARTCLKSEL 0x0128 |
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#define HW_UARTCLKUEN 0x012c |
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#define HW_I2S0CLKSEL 0x0130 |
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#define HW_I2S0CLKUEN 0x0134 |
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#define HW_I2S1CLKSEL 0x0138 |
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#define HW_I2S1CLKUEN 0x013c |
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#define HW_WDTCLKSEL 0x0160 |
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#define HW_WDTCLKUEN 0x0164 |
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#define HW_CLKOUTCLKSEL 0x0170 |
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#define HW_CLKOUTCLKUEN 0x0174 |
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#define HW_CPUCLKDIV 0x017c |
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#define HW_SYSAHBCLKDIV 0x0180 |
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#define HW_I2S0MCLKDIV 0x0190 |
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#define HW_I2S0SCLKDIV 0x0194 |
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#define HW_I2S1MCLKDIV 0x0188 |
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#define HW_I2S1SCLKDIV 0x018c |
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#define HW_UART0CLKDIV 0x0198 |
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#define HW_UART1CLKDIV 0x019c |
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#define HW_UART2CLKDIV 0x01a0 |
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#define HW_UART3CLKDIV 0x01a4 |
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#define HW_UART4CLKDIV 0x01a8 |
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#define HW_UART5CLKDIV 0x01ac |
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#define HW_UART6CLKDIV 0x01b0 |
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#define HW_UART7CLKDIV 0x01b4 |
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#define HW_UART8CLKDIV 0x01b8 |
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#define HW_UART9CLKDIV 0x01bc |
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#define HW_SPI0CLKDIV 0x01c0 |
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#define HW_SPI1CLKDIV 0x01c4 |
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#define HW_QUADSPICLKDIV 0x01c8 |
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#define HW_SSP0CLKDIV 0x01d0 |
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#define HW_NANDCLKDIV 0x01d4 |
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#define HW_TRACECLKDIV 0x01e0 |
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#define HW_CAMMCLKDIV 0x01e8 |
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#define HW_WDTCLKDIV 0x01ec |
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#define HW_CLKOUTCLKDIV 0x01f4 |
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#define HW_MACCLKDIV 0x01f8 |
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#define HW_LCDCLKDIV 0x01fc |
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#define HW_ADCANACLKDIV 0x0200 |
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static struct clk_hw_onecell_data *clk_data; |
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static DEFINE_SPINLOCK(asm9260_clk_lock); |
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struct asm9260_div_clk { |
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unsigned int idx; |
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const char *name; |
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const char *parent_name; |
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u32 reg; |
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}; |
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struct asm9260_gate_data { |
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unsigned int idx; |
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const char *name; |
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const char *parent_name; |
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u32 reg; |
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u8 bit_idx; |
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unsigned long flags; |
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}; |
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struct asm9260_mux_clock { |
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u8 mask; |
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u32 *table; |
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const char *name; |
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const char **parent_names; |
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u8 num_parents; |
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unsigned long offset; |
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unsigned long flags; |
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}; |
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static void __iomem *base; |
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static const struct asm9260_div_clk asm9260_div_clks[] __initconst = { |
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{ CLKID_SYS_CPU, "cpu_div", "main_gate", HW_CPUCLKDIV }, |
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{ CLKID_SYS_AHB, "ahb_div", "cpu_div", HW_SYSAHBCLKDIV }, |
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/* i2s has two deviders: one for only external mclk and internal |
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* devider for all clks. */ |
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{ CLKID_SYS_I2S0M, "i2s0m_div", "i2s0_mclk", HW_I2S0MCLKDIV }, |
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{ CLKID_SYS_I2S1M, "i2s1m_div", "i2s1_mclk", HW_I2S1MCLKDIV }, |
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{ CLKID_SYS_I2S0S, "i2s0s_div", "i2s0_gate", HW_I2S0SCLKDIV }, |
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{ CLKID_SYS_I2S1S, "i2s1s_div", "i2s0_gate", HW_I2S1SCLKDIV }, |
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{ CLKID_SYS_UART0, "uart0_div", "uart_gate", HW_UART0CLKDIV }, |
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{ CLKID_SYS_UART1, "uart1_div", "uart_gate", HW_UART1CLKDIV }, |
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{ CLKID_SYS_UART2, "uart2_div", "uart_gate", HW_UART2CLKDIV }, |
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{ CLKID_SYS_UART3, "uart3_div", "uart_gate", HW_UART3CLKDIV }, |
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{ CLKID_SYS_UART4, "uart4_div", "uart_gate", HW_UART4CLKDIV }, |
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{ CLKID_SYS_UART5, "uart5_div", "uart_gate", HW_UART5CLKDIV }, |
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{ CLKID_SYS_UART6, "uart6_div", "uart_gate", HW_UART6CLKDIV }, |
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{ CLKID_SYS_UART7, "uart7_div", "uart_gate", HW_UART7CLKDIV }, |
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{ CLKID_SYS_UART8, "uart8_div", "uart_gate", HW_UART8CLKDIV }, |
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{ CLKID_SYS_UART9, "uart9_div", "uart_gate", HW_UART9CLKDIV }, |
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{ CLKID_SYS_SPI0, "spi0_div", "main_gate", HW_SPI0CLKDIV }, |
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{ CLKID_SYS_SPI1, "spi1_div", "main_gate", HW_SPI1CLKDIV }, |
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{ CLKID_SYS_QUADSPI, "quadspi_div", "main_gate", HW_QUADSPICLKDIV }, |
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{ CLKID_SYS_SSP0, "ssp0_div", "main_gate", HW_SSP0CLKDIV }, |
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{ CLKID_SYS_NAND, "nand_div", "main_gate", HW_NANDCLKDIV }, |
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{ CLKID_SYS_TRACE, "trace_div", "main_gate", HW_TRACECLKDIV }, |
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{ CLKID_SYS_CAMM, "camm_div", "main_gate", HW_CAMMCLKDIV }, |
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{ CLKID_SYS_MAC, "mac_div", "main_gate", HW_MACCLKDIV }, |
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{ CLKID_SYS_LCD, "lcd_div", "main_gate", HW_LCDCLKDIV }, |
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{ CLKID_SYS_ADCANA, "adcana_div", "main_gate", HW_ADCANACLKDIV }, |
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{ CLKID_SYS_WDT, "wdt_div", "wdt_gate", HW_WDTCLKDIV }, |
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{ CLKID_SYS_CLKOUT, "clkout_div", "clkout_gate", HW_CLKOUTCLKDIV }, |
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}; |
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static const struct asm9260_gate_data asm9260_mux_gates[] __initconst = { |
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{ 0, "main_gate", "main_mux", HW_MAINCLKUEN, 0 }, |
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{ 0, "uart_gate", "uart_mux", HW_UARTCLKUEN, 0 }, |
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{ 0, "i2s0_gate", "i2s0_mux", HW_I2S0CLKUEN, 0 }, |
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{ 0, "i2s1_gate", "i2s1_mux", HW_I2S1CLKUEN, 0 }, |
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{ 0, "wdt_gate", "wdt_mux", HW_WDTCLKUEN, 0 }, |
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{ 0, "clkout_gate", "clkout_mux", HW_CLKOUTCLKUEN, 0 }, |
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}; |
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static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = { |
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/* ahb gates */ |
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{ CLKID_AHB_ROM, "rom", "ahb_div", |
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HW_AHBCLKCTRL0, 1, CLK_IGNORE_UNUSED}, |
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{ CLKID_AHB_RAM, "ram", "ahb_div", |
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HW_AHBCLKCTRL0, 2, CLK_IGNORE_UNUSED}, |
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{ CLKID_AHB_GPIO, "gpio", "ahb_div", |
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HW_AHBCLKCTRL0, 4 }, |
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{ CLKID_AHB_MAC, "mac", "ahb_div", |
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HW_AHBCLKCTRL0, 5 }, |
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{ CLKID_AHB_EMI, "emi", "ahb_div", |
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HW_AHBCLKCTRL0, 6, CLK_IGNORE_UNUSED}, |
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{ CLKID_AHB_USB0, "usb0", "ahb_div", |
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HW_AHBCLKCTRL0, 7 }, |
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{ CLKID_AHB_USB1, "usb1", "ahb_div", |
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HW_AHBCLKCTRL0, 8 }, |
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{ CLKID_AHB_DMA0, "dma0", "ahb_div", |
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HW_AHBCLKCTRL0, 9 }, |
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{ CLKID_AHB_DMA1, "dma1", "ahb_div", |
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HW_AHBCLKCTRL0, 10 }, |
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{ CLKID_AHB_UART0, "uart0", "ahb_div", |
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HW_AHBCLKCTRL0, 11 }, |
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{ CLKID_AHB_UART1, "uart1", "ahb_div", |
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HW_AHBCLKCTRL0, 12 }, |
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{ CLKID_AHB_UART2, "uart2", "ahb_div", |
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HW_AHBCLKCTRL0, 13 }, |
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{ CLKID_AHB_UART3, "uart3", "ahb_div", |
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HW_AHBCLKCTRL0, 14 }, |
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{ CLKID_AHB_UART4, "uart4", "ahb_div", |
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HW_AHBCLKCTRL0, 15 }, |
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{ CLKID_AHB_UART5, "uart5", "ahb_div", |
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HW_AHBCLKCTRL0, 16 }, |
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{ CLKID_AHB_UART6, "uart6", "ahb_div", |
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HW_AHBCLKCTRL0, 17 }, |
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{ CLKID_AHB_UART7, "uart7", "ahb_div", |
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HW_AHBCLKCTRL0, 18 }, |
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{ CLKID_AHB_UART8, "uart8", "ahb_div", |
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HW_AHBCLKCTRL0, 19 }, |
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{ CLKID_AHB_UART9, "uart9", "ahb_div", |
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HW_AHBCLKCTRL0, 20 }, |
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{ CLKID_AHB_I2S0, "i2s0", "ahb_div", |
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HW_AHBCLKCTRL0, 21 }, |
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{ CLKID_AHB_I2C0, "i2c0", "ahb_div", |
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HW_AHBCLKCTRL0, 22 }, |
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{ CLKID_AHB_I2C1, "i2c1", "ahb_div", |
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HW_AHBCLKCTRL0, 23 }, |
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{ CLKID_AHB_SSP0, "ssp0", "ahb_div", |
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HW_AHBCLKCTRL0, 24 }, |
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{ CLKID_AHB_IOCONFIG, "ioconf", "ahb_div", |
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HW_AHBCLKCTRL0, 25 }, |
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{ CLKID_AHB_WDT, "wdt", "ahb_div", |
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HW_AHBCLKCTRL0, 26 }, |
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{ CLKID_AHB_CAN0, "can0", "ahb_div", |
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HW_AHBCLKCTRL0, 27 }, |
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{ CLKID_AHB_CAN1, "can1", "ahb_div", |
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HW_AHBCLKCTRL0, 28 }, |
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{ CLKID_AHB_MPWM, "mpwm", "ahb_div", |
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HW_AHBCLKCTRL0, 29 }, |
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{ CLKID_AHB_SPI0, "spi0", "ahb_div", |
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HW_AHBCLKCTRL0, 30 }, |
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{ CLKID_AHB_SPI1, "spi1", "ahb_div", |
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HW_AHBCLKCTRL0, 31 }, |
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{ CLKID_AHB_QEI, "qei", "ahb_div", |
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HW_AHBCLKCTRL1, 0 }, |
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{ CLKID_AHB_QUADSPI0, "quadspi0", "ahb_div", |
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HW_AHBCLKCTRL1, 1 }, |
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{ CLKID_AHB_CAMIF, "capmif", "ahb_div", |
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HW_AHBCLKCTRL1, 2 }, |
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{ CLKID_AHB_LCDIF, "lcdif", "ahb_div", |
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HW_AHBCLKCTRL1, 3 }, |
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{ CLKID_AHB_TIMER0, "timer0", "ahb_div", |
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HW_AHBCLKCTRL1, 4 }, |
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{ CLKID_AHB_TIMER1, "timer1", "ahb_div", |
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HW_AHBCLKCTRL1, 5 }, |
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{ CLKID_AHB_TIMER2, "timer2", "ahb_div", |
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HW_AHBCLKCTRL1, 6 }, |
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{ CLKID_AHB_TIMER3, "timer3", "ahb_div", |
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HW_AHBCLKCTRL1, 7 }, |
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{ CLKID_AHB_IRQ, "irq", "ahb_div", |
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HW_AHBCLKCTRL1, 8, CLK_IGNORE_UNUSED}, |
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{ CLKID_AHB_RTC, "rtc", "ahb_div", |
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HW_AHBCLKCTRL1, 9 }, |
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{ CLKID_AHB_NAND, "nand", "ahb_div", |
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HW_AHBCLKCTRL1, 10 }, |
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{ CLKID_AHB_ADC0, "adc0", "ahb_div", |
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HW_AHBCLKCTRL1, 11 }, |
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{ CLKID_AHB_LED, "led", "ahb_div", |
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HW_AHBCLKCTRL1, 12 }, |
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{ CLKID_AHB_DAC0, "dac0", "ahb_div", |
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HW_AHBCLKCTRL1, 13 }, |
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{ CLKID_AHB_LCD, "lcd", "ahb_div", |
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HW_AHBCLKCTRL1, 14 }, |
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{ CLKID_AHB_I2S1, "i2s1", "ahb_div", |
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HW_AHBCLKCTRL1, 15 }, |
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{ CLKID_AHB_MAC1, "mac1", "ahb_div", |
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HW_AHBCLKCTRL1, 16 }, |
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}; |
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static const char __initdata *main_mux_p[] = { NULL, NULL }; |
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static const char __initdata *i2s0_mux_p[] = { NULL, NULL, "i2s0m_div"}; |
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static const char __initdata *i2s1_mux_p[] = { NULL, NULL, "i2s1m_div"}; |
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static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"}; |
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static u32 three_mux_table[] = {0, 1, 3}; |
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static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = { |
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{ 1, three_mux_table, "main_mux", main_mux_p, |
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ARRAY_SIZE(main_mux_p), HW_MAINCLKSEL, }, |
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{ 1, three_mux_table, "uart_mux", main_mux_p, |
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ARRAY_SIZE(main_mux_p), HW_UARTCLKSEL, }, |
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{ 1, three_mux_table, "wdt_mux", main_mux_p, |
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ARRAY_SIZE(main_mux_p), HW_WDTCLKSEL, }, |
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{ 3, three_mux_table, "i2s0_mux", i2s0_mux_p, |
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ARRAY_SIZE(i2s0_mux_p), HW_I2S0CLKSEL, }, |
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{ 3, three_mux_table, "i2s1_mux", i2s1_mux_p, |
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ARRAY_SIZE(i2s1_mux_p), HW_I2S1CLKSEL, }, |
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{ 3, three_mux_table, "clkout_mux", clkout_mux_p, |
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ARRAY_SIZE(clkout_mux_p), HW_CLKOUTCLKSEL, }, |
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}; |
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static void __init asm9260_acc_init(struct device_node *np) |
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{ |
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struct clk_hw *hw; |
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struct clk_hw **hws; |
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const char *ref_clk, *pll_clk = "pll"; |
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u32 rate; |
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int n; |
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clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL); |
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if (!clk_data) |
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return; |
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clk_data->num = MAX_CLKS; |
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hws = clk_data->hws; |
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base = of_io_request_and_map(np, 0, np->name); |
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if (IS_ERR(base)) |
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panic("%pOFn: unable to map resource", np); |
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/* register pll */ |
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rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000; |
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/* TODO: Convert to DT parent scheme */ |
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ref_clk = of_clk_get_parent_name(np, 0); |
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hw = __clk_hw_register_fixed_rate(NULL, NULL, pll_clk, |
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ref_clk, NULL, NULL, 0, rate, 0, |
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CLK_FIXED_RATE_PARENT_ACCURACY); |
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if (IS_ERR(hw)) |
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panic("%pOFn: can't register REFCLK. Check DT!", np); |
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for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) { |
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const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n]; |
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mc->parent_names[0] = ref_clk; |
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mc->parent_names[1] = pll_clk; |
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hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names, |
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mc->num_parents, mc->flags, base + mc->offset, |
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0, mc->mask, 0, mc->table, &asm9260_clk_lock); |
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} |
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/* clock mux gate cells */ |
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for (n = 0; n < ARRAY_SIZE(asm9260_mux_gates); n++) { |
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const struct asm9260_gate_data *gd = &asm9260_mux_gates[n]; |
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hw = clk_hw_register_gate(NULL, gd->name, |
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gd->parent_name, gd->flags | CLK_SET_RATE_PARENT, |
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base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock); |
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} |
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/* clock div cells */ |
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for (n = 0; n < ARRAY_SIZE(asm9260_div_clks); n++) { |
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const struct asm9260_div_clk *dc = &asm9260_div_clks[n]; |
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hws[dc->idx] = clk_hw_register_divider(NULL, dc->name, |
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dc->parent_name, CLK_SET_RATE_PARENT, |
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base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED, |
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&asm9260_clk_lock); |
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} |
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/* clock ahb gate cells */ |
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for (n = 0; n < ARRAY_SIZE(asm9260_ahb_gates); n++) { |
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const struct asm9260_gate_data *gd = &asm9260_ahb_gates[n]; |
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hws[gd->idx] = clk_hw_register_gate(NULL, gd->name, |
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gd->parent_name, gd->flags, base + gd->reg, |
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gd->bit_idx, 0, &asm9260_clk_lock); |
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} |
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/* check for errors on leaf clocks */ |
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for (n = 0; n < MAX_CLKS; n++) { |
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if (!IS_ERR(hws[n])) |
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continue; |
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pr_err("%pOF: Unable to register leaf clock %d\n", |
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np, n); |
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goto fail; |
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} |
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/* register clk-provider */ |
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of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); |
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return; |
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fail: |
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iounmap(base); |
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} |
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CLK_OF_DECLARE(asm9260_acc, "alphascale,asm9260-clock-controller", |
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asm9260_acc_init);
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