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525 lines
14 KiB
525 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* sata_svw.c - ServerWorks / Apple K2 SATA |
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* |
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* Maintained by: Benjamin Herrenschmidt <[email protected]> and |
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* Jeff Garzik <[email protected]> |
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* Please ALWAYS copy [email protected] |
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* on emails. |
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* |
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* Copyright 2003 Benjamin Herrenschmidt <[email protected]> |
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* |
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* Bits from Jeff Garzik, Copyright RedHat, Inc. |
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* |
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* This driver probably works with non-Apple versions of the |
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* Broadcom chipset... |
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* |
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* libata documentation is available via 'make {ps|pdf}docs', |
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* as Documentation/driver-api/libata.rst |
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* |
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* Hardware documentation available under NDA. |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/device.h> |
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#include <scsi/scsi_host.h> |
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#include <scsi/scsi_cmnd.h> |
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#include <scsi/scsi.h> |
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#include <linux/libata.h> |
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#include <linux/of.h> |
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|
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#define DRV_NAME "sata_svw" |
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#define DRV_VERSION "2.3" |
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enum { |
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/* ap->flags bits */ |
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K2_FLAG_SATA_8_PORTS = (1 << 24), |
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K2_FLAG_NO_ATAPI_DMA = (1 << 25), |
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K2_FLAG_BAR_POS_3 = (1 << 26), |
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|
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/* Taskfile registers offsets */ |
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K2_SATA_TF_CMD_OFFSET = 0x00, |
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K2_SATA_TF_DATA_OFFSET = 0x00, |
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K2_SATA_TF_ERROR_OFFSET = 0x04, |
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K2_SATA_TF_NSECT_OFFSET = 0x08, |
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K2_SATA_TF_LBAL_OFFSET = 0x0c, |
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K2_SATA_TF_LBAM_OFFSET = 0x10, |
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K2_SATA_TF_LBAH_OFFSET = 0x14, |
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K2_SATA_TF_DEVICE_OFFSET = 0x18, |
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K2_SATA_TF_CMDSTAT_OFFSET = 0x1c, |
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K2_SATA_TF_CTL_OFFSET = 0x20, |
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|
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/* DMA base */ |
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K2_SATA_DMA_CMD_OFFSET = 0x30, |
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|
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/* SCRs base */ |
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K2_SATA_SCR_STATUS_OFFSET = 0x40, |
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K2_SATA_SCR_ERROR_OFFSET = 0x44, |
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K2_SATA_SCR_CONTROL_OFFSET = 0x48, |
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|
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/* Others */ |
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K2_SATA_SICR1_OFFSET = 0x80, |
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K2_SATA_SICR2_OFFSET = 0x84, |
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K2_SATA_SIM_OFFSET = 0x88, |
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|
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/* Port stride */ |
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K2_SATA_PORT_OFFSET = 0x100, |
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|
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chip_svw4 = 0, |
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chip_svw8 = 1, |
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chip_svw42 = 2, /* bar 3 */ |
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chip_svw43 = 3, /* bar 5 */ |
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}; |
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static u8 k2_stat_check_status(struct ata_port *ap); |
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static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
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{ |
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u8 cmnd = qc->scsicmd->cmnd[0]; |
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|
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if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA) |
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return -1; /* ATAPI DMA not supported */ |
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else { |
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switch (cmnd) { |
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case READ_10: |
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case READ_12: |
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case READ_16: |
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case WRITE_10: |
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case WRITE_12: |
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case WRITE_16: |
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return 0; |
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default: |
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return -1; |
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} |
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} |
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} |
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static int k2_sata_scr_read(struct ata_link *link, |
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unsigned int sc_reg, u32 *val) |
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{ |
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if (sc_reg > SCR_CONTROL) |
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return -EINVAL; |
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*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
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return 0; |
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} |
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static int k2_sata_scr_write(struct ata_link *link, |
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unsigned int sc_reg, u32 val) |
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{ |
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if (sc_reg > SCR_CONTROL) |
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return -EINVAL; |
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writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4)); |
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return 0; |
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} |
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static int k2_sata_softreset(struct ata_link *link, |
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unsigned int *class, unsigned long deadline) |
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{ |
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u8 dmactl; |
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void __iomem *mmio = link->ap->ioaddr.bmdma_addr; |
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dmactl = readb(mmio + ATA_DMA_CMD); |
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|
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/* Clear the start bit */ |
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if (dmactl & ATA_DMA_START) { |
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dmactl &= ~ATA_DMA_START; |
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writeb(dmactl, mmio + ATA_DMA_CMD); |
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} |
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return ata_sff_softreset(link, class, deadline); |
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} |
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static int k2_sata_hardreset(struct ata_link *link, |
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unsigned int *class, unsigned long deadline) |
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{ |
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u8 dmactl; |
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void __iomem *mmio = link->ap->ioaddr.bmdma_addr; |
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dmactl = readb(mmio + ATA_DMA_CMD); |
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/* Clear the start bit */ |
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if (dmactl & ATA_DMA_START) { |
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dmactl &= ~ATA_DMA_START; |
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writeb(dmactl, mmio + ATA_DMA_CMD); |
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} |
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return sata_sff_hardreset(link, class, deadline); |
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} |
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static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
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{ |
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struct ata_ioports *ioaddr = &ap->ioaddr; |
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; |
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|
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if (tf->ctl != ap->last_ctl) { |
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writeb(tf->ctl, ioaddr->ctl_addr); |
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ap->last_ctl = tf->ctl; |
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ata_wait_idle(ap); |
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} |
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { |
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writew(tf->feature | (((u16)tf->hob_feature) << 8), |
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ioaddr->feature_addr); |
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writew(tf->nsect | (((u16)tf->hob_nsect) << 8), |
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ioaddr->nsect_addr); |
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writew(tf->lbal | (((u16)tf->hob_lbal) << 8), |
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ioaddr->lbal_addr); |
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writew(tf->lbam | (((u16)tf->hob_lbam) << 8), |
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ioaddr->lbam_addr); |
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writew(tf->lbah | (((u16)tf->hob_lbah) << 8), |
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ioaddr->lbah_addr); |
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} else if (is_addr) { |
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writew(tf->feature, ioaddr->feature_addr); |
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writew(tf->nsect, ioaddr->nsect_addr); |
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writew(tf->lbal, ioaddr->lbal_addr); |
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writew(tf->lbam, ioaddr->lbam_addr); |
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writew(tf->lbah, ioaddr->lbah_addr); |
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} |
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if (tf->flags & ATA_TFLAG_DEVICE) |
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writeb(tf->device, ioaddr->device_addr); |
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ata_wait_idle(ap); |
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} |
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static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
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{ |
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struct ata_ioports *ioaddr = &ap->ioaddr; |
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u16 nsect, lbal, lbam, lbah, feature; |
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|
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tf->command = k2_stat_check_status(ap); |
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tf->device = readw(ioaddr->device_addr); |
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feature = readw(ioaddr->error_addr); |
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nsect = readw(ioaddr->nsect_addr); |
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lbal = readw(ioaddr->lbal_addr); |
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lbam = readw(ioaddr->lbam_addr); |
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lbah = readw(ioaddr->lbah_addr); |
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tf->feature = feature; |
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tf->nsect = nsect; |
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tf->lbal = lbal; |
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tf->lbam = lbam; |
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tf->lbah = lbah; |
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if (tf->flags & ATA_TFLAG_LBA48) { |
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tf->hob_feature = feature >> 8; |
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tf->hob_nsect = nsect >> 8; |
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tf->hob_lbal = lbal >> 8; |
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tf->hob_lbam = lbam >> 8; |
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tf->hob_lbah = lbah >> 8; |
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} |
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} |
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/** |
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* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO) |
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* @qc: Info associated with this ATA transaction. |
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* |
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* LOCKING: |
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* spin_lock_irqsave(host lock) |
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*/ |
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static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc) |
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{ |
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struct ata_port *ap = qc->ap; |
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); |
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u8 dmactl; |
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void __iomem *mmio = ap->ioaddr.bmdma_addr; |
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|
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/* load PRD table addr. */ |
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mb(); /* make sure PRD table writes are visible to controller */ |
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writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS); |
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/* specify data direction, triple-check start bit is clear */ |
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dmactl = readb(mmio + ATA_DMA_CMD); |
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dmactl &= ~(ATA_DMA_WR | ATA_DMA_START); |
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if (!rw) |
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dmactl |= ATA_DMA_WR; |
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writeb(dmactl, mmio + ATA_DMA_CMD); |
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/* issue r/w command if this is not a ATA DMA command*/ |
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if (qc->tf.protocol != ATA_PROT_DMA) |
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ap->ops->sff_exec_command(ap, &qc->tf); |
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} |
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/** |
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* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO) |
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* @qc: Info associated with this ATA transaction. |
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* |
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* LOCKING: |
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* spin_lock_irqsave(host lock) |
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*/ |
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static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc) |
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{ |
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struct ata_port *ap = qc->ap; |
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void __iomem *mmio = ap->ioaddr.bmdma_addr; |
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u8 dmactl; |
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/* start host DMA transaction */ |
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dmactl = readb(mmio + ATA_DMA_CMD); |
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writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD); |
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/* This works around possible data corruption. |
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|
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On certain SATA controllers that can be seen when the r/w |
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command is given to the controller before the host DMA is |
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started. |
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|
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On a Read command, the controller would initiate the |
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command to the drive even before it sees the DMA |
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start. When there are very fast drives connected to the |
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controller, or when the data request hits in the drive |
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cache, there is the possibility that the drive returns a |
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part or all of the requested data to the controller before |
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the DMA start is issued. In this case, the controller |
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would become confused as to what to do with the data. In |
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the worst case when all the data is returned back to the |
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controller, the controller could hang. In other cases it |
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could return partial data returning in data |
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corruption. This problem has been seen in PPC systems and |
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can also appear on an system with very fast disks, where |
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the SATA controller is sitting behind a number of bridges, |
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and hence there is significant latency between the r/w |
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command and the start command. */ |
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/* issue r/w command if the access is to ATA */ |
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if (qc->tf.protocol == ATA_PROT_DMA) |
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ap->ops->sff_exec_command(ap, &qc->tf); |
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} |
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static u8 k2_stat_check_status(struct ata_port *ap) |
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{ |
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return readl(ap->ioaddr.status_addr); |
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} |
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static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost) |
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{ |
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struct ata_port *ap; |
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struct device_node *np; |
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int index; |
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/* Find the ata_port */ |
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ap = ata_shost_to_port(shost); |
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if (ap == NULL) |
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return 0; |
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/* Find the OF node for the PCI device proper */ |
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np = pci_device_to_OF_node(to_pci_dev(ap->host->dev)); |
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if (np == NULL) |
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return 0; |
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/* Match it to a port node */ |
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index = (ap == ap->host->ports[0]) ? 0 : 1; |
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for (np = np->child; np != NULL; np = np->sibling) { |
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const u32 *reg = of_get_property(np, "reg", NULL); |
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if (!reg) |
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continue; |
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if (index == *reg) { |
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seq_printf(m, "devspec: %pOF\n", np); |
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break; |
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} |
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} |
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return 0; |
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} |
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static struct scsi_host_template k2_sata_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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.show_info = k2_sata_show_info, |
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}; |
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static struct ata_port_operations k2_sata_ops = { |
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.inherits = &ata_bmdma_port_ops, |
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.softreset = k2_sata_softreset, |
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.hardreset = k2_sata_hardreset, |
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.sff_tf_load = k2_sata_tf_load, |
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.sff_tf_read = k2_sata_tf_read, |
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.sff_check_status = k2_stat_check_status, |
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.check_atapi_dma = k2_sata_check_atapi_dma, |
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.bmdma_setup = k2_bmdma_setup_mmio, |
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.bmdma_start = k2_bmdma_start_mmio, |
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.scr_read = k2_sata_scr_read, |
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.scr_write = k2_sata_scr_write, |
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}; |
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static const struct ata_port_info k2_port_info[] = { |
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/* chip_svw4 */ |
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{ |
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.flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA6, |
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.port_ops = &k2_sata_ops, |
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}, |
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/* chip_svw8 */ |
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{ |
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.flags = ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA | |
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K2_FLAG_SATA_8_PORTS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA6, |
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.port_ops = &k2_sata_ops, |
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}, |
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/* chip_svw42 */ |
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{ |
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.flags = ATA_FLAG_SATA | K2_FLAG_BAR_POS_3, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA6, |
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.port_ops = &k2_sata_ops, |
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}, |
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/* chip_svw43 */ |
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{ |
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.flags = ATA_FLAG_SATA, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA6, |
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.port_ops = &k2_sata_ops, |
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}, |
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}; |
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static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base) |
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{ |
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port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET; |
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port->data_addr = base + K2_SATA_TF_DATA_OFFSET; |
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port->feature_addr = |
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port->error_addr = base + K2_SATA_TF_ERROR_OFFSET; |
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port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET; |
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port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET; |
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port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET; |
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port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET; |
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port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET; |
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port->command_addr = |
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port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET; |
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port->altstatus_addr = |
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port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET; |
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port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET; |
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port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET; |
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} |
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static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
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{ |
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const struct ata_port_info *ppi[] = |
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{ &k2_port_info[ent->driver_data], NULL }; |
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struct ata_host *host; |
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void __iomem *mmio_base; |
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int n_ports, i, rc, bar_pos; |
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|
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ata_print_version_once(&pdev->dev, DRV_VERSION); |
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/* allocate host */ |
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n_ports = 4; |
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if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS) |
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n_ports = 8; |
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host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
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if (!host) |
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return -ENOMEM; |
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bar_pos = 5; |
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if (ppi[0]->flags & K2_FLAG_BAR_POS_3) |
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bar_pos = 3; |
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/* |
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* If this driver happens to only be useful on Apple's K2, then |
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* we should check that here as it has a normal Serverworks ID |
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*/ |
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rc = pcim_enable_device(pdev); |
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if (rc) |
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return rc; |
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|
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/* |
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* Check if we have resources mapped at all (second function may |
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* have been disabled by firmware) |
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*/ |
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if (pci_resource_len(pdev, bar_pos) == 0) { |
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/* In IDE mode we need to pin the device to ensure that |
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pcim_release does not clear the busmaster bit in config |
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space, clearing causes busmaster DMA to fail on |
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ports 3 & 4 */ |
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pcim_pin_device(pdev); |
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return -ENODEV; |
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} |
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|
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/* Request and iomap PCI regions */ |
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rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME); |
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if (rc == -EBUSY) |
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pcim_pin_device(pdev); |
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if (rc) |
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return rc; |
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host->iomap = pcim_iomap_table(pdev); |
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mmio_base = host->iomap[bar_pos]; |
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|
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/* different controllers have different number of ports - currently 4 or 8 */ |
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/* All ports are on the same function. Multi-function device is no |
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* longer available. This should not be seen in any system. */ |
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for (i = 0; i < host->n_ports; i++) { |
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struct ata_port *ap = host->ports[i]; |
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unsigned int offset = i * K2_SATA_PORT_OFFSET; |
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|
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k2_sata_setup_port(&ap->ioaddr, mmio_base + offset); |
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|
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ata_port_pbar_desc(ap, 5, -1, "mmio"); |
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ata_port_pbar_desc(ap, 5, offset, "port"); |
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} |
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rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); |
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if (rc) |
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return rc; |
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|
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/* Clear a magic bit in SCR1 according to Darwin, those help |
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* some funky seagate drives (though so far, those were already |
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* set by the firmware on the machines I had access to) |
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*/ |
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writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000, |
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mmio_base + K2_SATA_SICR1_OFFSET); |
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|
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/* Clear SATA error & interrupts we don't use */ |
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writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET); |
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writel(0x0, mmio_base + K2_SATA_SIM_OFFSET); |
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|
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pci_set_master(pdev); |
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return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, |
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IRQF_SHARED, &k2_sata_sht); |
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} |
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|
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/* 0x240 is device ID for Apple K2 device |
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* 0x241 is device ID for Serverworks Frodo4 |
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* 0x242 is device ID for Serverworks Frodo8 |
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* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA |
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* controller |
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* */ |
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static const struct pci_device_id k2_sata_pci_tbl[] = { |
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{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 }, |
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{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 }, |
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{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 }, |
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{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 }, |
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{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 }, |
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{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 }, |
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{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 }, |
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|
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{ } |
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}; |
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|
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static struct pci_driver k2_sata_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = k2_sata_pci_tbl, |
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.probe = k2_sata_init_one, |
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.remove = ata_pci_remove_one, |
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}; |
|
|
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module_pci_driver(k2_sata_pci_driver); |
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|
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MODULE_AUTHOR("Benjamin Herrenschmidt"); |
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MODULE_DESCRIPTION("low-level driver for K2 SATA controller"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl); |
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MODULE_VERSION(DRV_VERSION);
|
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|