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808 lines
21 KiB
808 lines
21 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* sata_sil.c - Silicon Image SATA |
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* |
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* Maintained by: Tejun Heo <[email protected]> |
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* Please ALWAYS copy [email protected] |
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* on emails. |
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* |
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* Copyright 2003-2005 Red Hat, Inc. |
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* Copyright 2003 Benjamin Herrenschmidt |
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* |
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* libata documentation is available via 'make {ps|pdf}docs', |
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* as Documentation/driver-api/libata.rst |
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* |
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* Documentation for SiI 3112: |
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* http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2 |
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* |
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* Other errata and documentation available under NDA. |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/device.h> |
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#include <scsi/scsi_host.h> |
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#include <linux/libata.h> |
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#include <linux/dmi.h> |
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#define DRV_NAME "sata_sil" |
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#define DRV_VERSION "2.4" |
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#define SIL_DMA_BOUNDARY 0x7fffffffUL |
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enum { |
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SIL_MMIO_BAR = 5, |
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|
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/* |
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* host flags |
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*/ |
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SIL_FLAG_NO_SATA_IRQ = (1 << 28), |
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SIL_FLAG_RERR_ON_DMA_ACT = (1 << 29), |
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SIL_FLAG_MOD15WRITE = (1 << 30), |
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SIL_DFL_PORT_FLAGS = ATA_FLAG_SATA, |
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|
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/* |
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* Controller IDs |
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*/ |
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sil_3112 = 0, |
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sil_3112_no_sata_irq = 1, |
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sil_3512 = 2, |
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sil_3114 = 3, |
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|
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/* |
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* Register offsets |
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*/ |
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SIL_SYSCFG = 0x48, |
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|
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/* |
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* Register bits |
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*/ |
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/* SYSCFG */ |
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SIL_MASK_IDE0_INT = (1 << 22), |
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SIL_MASK_IDE1_INT = (1 << 23), |
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SIL_MASK_IDE2_INT = (1 << 24), |
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SIL_MASK_IDE3_INT = (1 << 25), |
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SIL_MASK_2PORT = SIL_MASK_IDE0_INT | SIL_MASK_IDE1_INT, |
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SIL_MASK_4PORT = SIL_MASK_2PORT | |
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SIL_MASK_IDE2_INT | SIL_MASK_IDE3_INT, |
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|
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/* BMDMA/BMDMA2 */ |
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SIL_INTR_STEERING = (1 << 1), |
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SIL_DMA_ENABLE = (1 << 0), /* DMA run switch */ |
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SIL_DMA_RDWR = (1 << 3), /* DMA Rd-Wr */ |
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SIL_DMA_SATA_IRQ = (1 << 4), /* OR of all SATA IRQs */ |
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SIL_DMA_ACTIVE = (1 << 16), /* DMA running */ |
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SIL_DMA_ERROR = (1 << 17), /* PCI bus error */ |
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SIL_DMA_COMPLETE = (1 << 18), /* cmd complete / IRQ pending */ |
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SIL_DMA_N_SATA_IRQ = (1 << 6), /* SATA_IRQ for the next channel */ |
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SIL_DMA_N_ACTIVE = (1 << 24), /* ACTIVE for the next channel */ |
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SIL_DMA_N_ERROR = (1 << 25), /* ERROR for the next channel */ |
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SIL_DMA_N_COMPLETE = (1 << 26), /* COMPLETE for the next channel */ |
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/* SIEN */ |
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SIL_SIEN_N = (1 << 16), /* triggered by SError.N */ |
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/* |
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* Others |
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*/ |
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SIL_QUIRK_MOD15WRITE = (1 << 0), |
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SIL_QUIRK_UDMA5MAX = (1 << 1), |
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}; |
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static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
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#ifdef CONFIG_PM_SLEEP |
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static int sil_pci_device_resume(struct pci_dev *pdev); |
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#endif |
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static void sil_dev_config(struct ata_device *dev); |
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static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
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static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); |
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static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed); |
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static enum ata_completion_errors sil_qc_prep(struct ata_queued_cmd *qc); |
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static void sil_bmdma_setup(struct ata_queued_cmd *qc); |
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static void sil_bmdma_start(struct ata_queued_cmd *qc); |
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static void sil_bmdma_stop(struct ata_queued_cmd *qc); |
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static void sil_freeze(struct ata_port *ap); |
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static void sil_thaw(struct ata_port *ap); |
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static const struct pci_device_id sil_pci_tbl[] = { |
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{ PCI_VDEVICE(CMD, 0x3112), sil_3112 }, |
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{ PCI_VDEVICE(CMD, 0x0240), sil_3112 }, |
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{ PCI_VDEVICE(CMD, 0x3512), sil_3512 }, |
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{ PCI_VDEVICE(CMD, 0x3114), sil_3114 }, |
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{ PCI_VDEVICE(ATI, 0x436e), sil_3112 }, |
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{ PCI_VDEVICE(ATI, 0x4379), sil_3112_no_sata_irq }, |
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{ PCI_VDEVICE(ATI, 0x437a), sil_3112_no_sata_irq }, |
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{ } /* terminate list */ |
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}; |
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/* TODO firmware versions should be added - eric */ |
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static const struct sil_drivelist { |
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const char *product; |
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unsigned int quirk; |
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} sil_blacklist [] = { |
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{ "ST320012AS", SIL_QUIRK_MOD15WRITE }, |
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{ "ST330013AS", SIL_QUIRK_MOD15WRITE }, |
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{ "ST340017AS", SIL_QUIRK_MOD15WRITE }, |
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{ "ST360015AS", SIL_QUIRK_MOD15WRITE }, |
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{ "ST380023AS", SIL_QUIRK_MOD15WRITE }, |
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{ "ST3120023AS", SIL_QUIRK_MOD15WRITE }, |
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{ "ST340014ASL", SIL_QUIRK_MOD15WRITE }, |
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{ "ST360014ASL", SIL_QUIRK_MOD15WRITE }, |
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{ "ST380011ASL", SIL_QUIRK_MOD15WRITE }, |
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{ "ST3120022ASL", SIL_QUIRK_MOD15WRITE }, |
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{ "ST3160021ASL", SIL_QUIRK_MOD15WRITE }, |
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{ "TOSHIBA MK2561GSYN", SIL_QUIRK_MOD15WRITE }, |
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{ "Maxtor 4D060H3", SIL_QUIRK_UDMA5MAX }, |
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{ } |
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}; |
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static struct pci_driver sil_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = sil_pci_tbl, |
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.probe = sil_init_one, |
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.remove = ata_pci_remove_one, |
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#ifdef CONFIG_PM_SLEEP |
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.suspend = ata_pci_device_suspend, |
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.resume = sil_pci_device_resume, |
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#endif |
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}; |
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static struct scsi_host_template sil_sht = { |
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ATA_BASE_SHT(DRV_NAME), |
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/** These controllers support Large Block Transfer which allows |
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transfer chunks up to 2GB and which cross 64KB boundaries, |
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therefore the DMA limits are more relaxed than standard ATA SFF. */ |
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.dma_boundary = SIL_DMA_BOUNDARY, |
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.sg_tablesize = ATA_MAX_PRD |
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}; |
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static struct ata_port_operations sil_ops = { |
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.inherits = &ata_bmdma32_port_ops, |
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.dev_config = sil_dev_config, |
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.set_mode = sil_set_mode, |
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.bmdma_setup = sil_bmdma_setup, |
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.bmdma_start = sil_bmdma_start, |
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.bmdma_stop = sil_bmdma_stop, |
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.qc_prep = sil_qc_prep, |
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.freeze = sil_freeze, |
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.thaw = sil_thaw, |
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.scr_read = sil_scr_read, |
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.scr_write = sil_scr_write, |
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}; |
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static const struct ata_port_info sil_port_info[] = { |
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/* sil_3112 */ |
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{ |
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.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA5, |
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.port_ops = &sil_ops, |
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}, |
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/* sil_3112_no_sata_irq */ |
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{ |
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.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_MOD15WRITE | |
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SIL_FLAG_NO_SATA_IRQ, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA5, |
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.port_ops = &sil_ops, |
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}, |
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/* sil_3512 */ |
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{ |
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.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA5, |
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.port_ops = &sil_ops, |
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}, |
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/* sil_3114 */ |
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{ |
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.flags = SIL_DFL_PORT_FLAGS | SIL_FLAG_RERR_ON_DMA_ACT, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA2, |
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.udma_mask = ATA_UDMA5, |
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.port_ops = &sil_ops, |
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}, |
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}; |
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/* per-port register offsets */ |
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/* TODO: we can probably calculate rather than use a table */ |
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static const struct { |
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unsigned long tf; /* ATA taskfile register block */ |
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unsigned long ctl; /* ATA control/altstatus register block */ |
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unsigned long bmdma; /* DMA register block */ |
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unsigned long bmdma2; /* DMA register block #2 */ |
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unsigned long fifo_cfg; /* FIFO Valid Byte Count and Control */ |
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unsigned long scr; /* SATA control register block */ |
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unsigned long sien; /* SATA Interrupt Enable register */ |
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unsigned long xfer_mode;/* data transfer mode register */ |
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unsigned long sfis_cfg; /* SATA FIS reception config register */ |
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} sil_port[] = { |
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/* port 0 ... */ |
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/* tf ctl bmdma bmdma2 fifo scr sien mode sfis */ |
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{ 0x80, 0x8A, 0x0, 0x10, 0x40, 0x100, 0x148, 0xb4, 0x14c }, |
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{ 0xC0, 0xCA, 0x8, 0x18, 0x44, 0x180, 0x1c8, 0xf4, 0x1cc }, |
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{ 0x280, 0x28A, 0x200, 0x210, 0x240, 0x300, 0x348, 0x2b4, 0x34c }, |
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{ 0x2C0, 0x2CA, 0x208, 0x218, 0x244, 0x380, 0x3c8, 0x2f4, 0x3cc }, |
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/* ... port 3 */ |
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}; |
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MODULE_AUTHOR("Jeff Garzik"); |
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MODULE_DESCRIPTION("low-level driver for Silicon Image SATA controller"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, sil_pci_tbl); |
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MODULE_VERSION(DRV_VERSION); |
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static int slow_down; |
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module_param(slow_down, int, 0444); |
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MODULE_PARM_DESC(slow_down, "Sledgehammer used to work around random problems, by limiting commands to 15 sectors (0=off, 1=on)"); |
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static void sil_bmdma_stop(struct ata_queued_cmd *qc) |
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{ |
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struct ata_port *ap = qc->ap; |
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void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
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void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; |
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/* clear start/stop bit - can safely always write 0 */ |
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iowrite8(0, bmdma2); |
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/* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ |
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ata_sff_dma_pause(ap); |
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} |
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static void sil_bmdma_setup(struct ata_queued_cmd *qc) |
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{ |
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struct ata_port *ap = qc->ap; |
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void __iomem *bmdma = ap->ioaddr.bmdma_addr; |
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/* load PRD table addr. */ |
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iowrite32(ap->bmdma_prd_dma, bmdma + ATA_DMA_TABLE_OFS); |
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/* issue r/w command */ |
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ap->ops->sff_exec_command(ap, &qc->tf); |
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} |
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static void sil_bmdma_start(struct ata_queued_cmd *qc) |
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{ |
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); |
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struct ata_port *ap = qc->ap; |
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void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
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void __iomem *bmdma2 = mmio_base + sil_port[ap->port_no].bmdma2; |
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u8 dmactl = ATA_DMA_START; |
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/* set transfer direction, start host DMA transaction |
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Note: For Large Block Transfer to work, the DMA must be started |
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using the bmdma2 register. */ |
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if (!rw) |
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dmactl |= ATA_DMA_WR; |
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iowrite8(dmactl, bmdma2); |
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} |
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/* The way God intended PCI IDE scatter/gather lists to look and behave... */ |
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static void sil_fill_sg(struct ata_queued_cmd *qc) |
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{ |
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struct scatterlist *sg; |
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struct ata_port *ap = qc->ap; |
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struct ata_bmdma_prd *prd, *last_prd = NULL; |
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unsigned int si; |
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prd = &ap->bmdma_prd[0]; |
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for_each_sg(qc->sg, sg, qc->n_elem, si) { |
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/* Note h/w doesn't support 64-bit, so we unconditionally |
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* truncate dma_addr_t to u32. |
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*/ |
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u32 addr = (u32) sg_dma_address(sg); |
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u32 sg_len = sg_dma_len(sg); |
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prd->addr = cpu_to_le32(addr); |
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prd->flags_len = cpu_to_le32(sg_len); |
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VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len); |
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last_prd = prd; |
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prd++; |
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} |
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if (likely(last_prd)) |
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last_prd->flags_len |= cpu_to_le32(ATA_PRD_EOT); |
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} |
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static enum ata_completion_errors sil_qc_prep(struct ata_queued_cmd *qc) |
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{ |
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if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
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return AC_ERR_OK; |
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sil_fill_sg(qc); |
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return AC_ERR_OK; |
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} |
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static unsigned char sil_get_device_cache_line(struct pci_dev *pdev) |
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{ |
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u8 cache_line = 0; |
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pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line); |
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return cache_line; |
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} |
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|
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/** |
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* sil_set_mode - wrap set_mode functions |
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* @link: link to set up |
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* @r_failed: returned device when we fail |
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* |
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* Wrap the libata method for device setup as after the setup we need |
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* to inspect the results and do some configuration work |
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*/ |
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static int sil_set_mode(struct ata_link *link, struct ata_device **r_failed) |
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{ |
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struct ata_port *ap = link->ap; |
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void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
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void __iomem *addr = mmio_base + sil_port[ap->port_no].xfer_mode; |
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struct ata_device *dev; |
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u32 tmp, dev_mode[2] = { }; |
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int rc; |
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rc = ata_do_set_mode(link, r_failed); |
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if (rc) |
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return rc; |
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ata_for_each_dev(dev, link, ALL) { |
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if (!ata_dev_enabled(dev)) |
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dev_mode[dev->devno] = 0; /* PIO0/1/2 */ |
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else if (dev->flags & ATA_DFLAG_PIO) |
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dev_mode[dev->devno] = 1; /* PIO3/4 */ |
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else |
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dev_mode[dev->devno] = 3; /* UDMA */ |
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/* value 2 indicates MDMA */ |
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} |
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tmp = readl(addr); |
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tmp &= ~((1<<5) | (1<<4) | (1<<1) | (1<<0)); |
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tmp |= dev_mode[0]; |
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tmp |= (dev_mode[1] << 4); |
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writel(tmp, addr); |
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readl(addr); /* flush */ |
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return 0; |
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} |
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static inline void __iomem *sil_scr_addr(struct ata_port *ap, |
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unsigned int sc_reg) |
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{ |
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void __iomem *offset = ap->ioaddr.scr_addr; |
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switch (sc_reg) { |
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case SCR_STATUS: |
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return offset + 4; |
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case SCR_ERROR: |
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return offset + 8; |
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case SCR_CONTROL: |
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return offset; |
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default: |
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/* do nothing */ |
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break; |
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} |
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return NULL; |
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} |
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static int sil_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) |
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{ |
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void __iomem *mmio = sil_scr_addr(link->ap, sc_reg); |
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if (mmio) { |
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*val = readl(mmio); |
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return 0; |
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} |
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return -EINVAL; |
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} |
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static int sil_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) |
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{ |
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void __iomem *mmio = sil_scr_addr(link->ap, sc_reg); |
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if (mmio) { |
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writel(val, mmio); |
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return 0; |
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} |
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return -EINVAL; |
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} |
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static void sil_host_intr(struct ata_port *ap, u32 bmdma2) |
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{ |
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struct ata_eh_info *ehi = &ap->link.eh_info; |
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struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); |
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u8 status; |
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if (unlikely(bmdma2 & SIL_DMA_SATA_IRQ)) { |
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u32 serror = 0xffffffff; |
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/* SIEN doesn't mask SATA IRQs on some 3112s. Those |
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* controllers continue to assert IRQ as long as |
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* SError bits are pending. Clear SError immediately. |
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*/ |
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sil_scr_read(&ap->link, SCR_ERROR, &serror); |
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sil_scr_write(&ap->link, SCR_ERROR, serror); |
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/* Sometimes spurious interrupts occur, double check |
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* it's PHYRDY CHG. |
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*/ |
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if (serror & SERR_PHYRDY_CHG) { |
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ap->link.eh_info.serror |= serror; |
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goto freeze; |
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} |
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if (!(bmdma2 & SIL_DMA_COMPLETE)) |
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return; |
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} |
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if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { |
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/* this sometimes happens, just clear IRQ */ |
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ap->ops->sff_check_status(ap); |
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return; |
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} |
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|
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/* Check whether we are expecting interrupt in this state */ |
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switch (ap->hsm_task_state) { |
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case HSM_ST_FIRST: |
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/* Some pre-ATAPI-4 devices assert INTRQ |
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* at this state when ready to receive CDB. |
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*/ |
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|
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/* Check the ATA_DFLAG_CDB_INTR flag is enough here. |
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* The flag was turned on only for atapi devices. No |
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* need to check ata_is_atapi(qc->tf.protocol) again. |
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*/ |
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if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) |
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goto err_hsm; |
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break; |
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case HSM_ST_LAST: |
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if (ata_is_dma(qc->tf.protocol)) { |
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/* clear DMA-Start bit */ |
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ap->ops->bmdma_stop(qc); |
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if (bmdma2 & SIL_DMA_ERROR) { |
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qc->err_mask |= AC_ERR_HOST_BUS; |
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ap->hsm_task_state = HSM_ST_ERR; |
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} |
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} |
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break; |
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case HSM_ST: |
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break; |
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default: |
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goto err_hsm; |
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} |
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/* check main status, clearing INTRQ */ |
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status = ap->ops->sff_check_status(ap); |
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if (unlikely(status & ATA_BUSY)) |
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goto err_hsm; |
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|
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/* ack bmdma irq events */ |
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ata_bmdma_irq_clear(ap); |
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|
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/* kick HSM in the ass */ |
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ata_sff_hsm_move(ap, qc, status, 0); |
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if (unlikely(qc->err_mask) && ata_is_dma(qc->tf.protocol)) |
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ata_ehi_push_desc(ehi, "BMDMA2 stat 0x%x", bmdma2); |
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return; |
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err_hsm: |
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qc->err_mask |= AC_ERR_HSM; |
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freeze: |
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ata_port_freeze(ap); |
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} |
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static irqreturn_t sil_interrupt(int irq, void *dev_instance) |
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{ |
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struct ata_host *host = dev_instance; |
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void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; |
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int handled = 0; |
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int i; |
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spin_lock(&host->lock); |
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|
|
for (i = 0; i < host->n_ports; i++) { |
|
struct ata_port *ap = host->ports[i]; |
|
u32 bmdma2 = readl(mmio_base + sil_port[ap->port_no].bmdma2); |
|
|
|
/* turn off SATA_IRQ if not supported */ |
|
if (ap->flags & SIL_FLAG_NO_SATA_IRQ) |
|
bmdma2 &= ~SIL_DMA_SATA_IRQ; |
|
|
|
if (bmdma2 == 0xffffffff || |
|
!(bmdma2 & (SIL_DMA_COMPLETE | SIL_DMA_SATA_IRQ))) |
|
continue; |
|
|
|
sil_host_intr(ap, bmdma2); |
|
handled = 1; |
|
} |
|
|
|
spin_unlock(&host->lock); |
|
|
|
return IRQ_RETVAL(handled); |
|
} |
|
|
|
static void sil_freeze(struct ata_port *ap) |
|
{ |
|
void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
|
u32 tmp; |
|
|
|
/* global IRQ mask doesn't block SATA IRQ, turn off explicitly */ |
|
writel(0, mmio_base + sil_port[ap->port_no].sien); |
|
|
|
/* plug IRQ */ |
|
tmp = readl(mmio_base + SIL_SYSCFG); |
|
tmp |= SIL_MASK_IDE0_INT << ap->port_no; |
|
writel(tmp, mmio_base + SIL_SYSCFG); |
|
readl(mmio_base + SIL_SYSCFG); /* flush */ |
|
|
|
/* Ensure DMA_ENABLE is off. |
|
* |
|
* This is because the controller will not give us access to the |
|
* taskfile registers while a DMA is in progress |
|
*/ |
|
iowrite8(ioread8(ap->ioaddr.bmdma_addr) & ~SIL_DMA_ENABLE, |
|
ap->ioaddr.bmdma_addr); |
|
|
|
/* According to ata_bmdma_stop, an HDMA transition requires |
|
* on PIO cycle. But we can't read a taskfile register. |
|
*/ |
|
ioread8(ap->ioaddr.bmdma_addr); |
|
} |
|
|
|
static void sil_thaw(struct ata_port *ap) |
|
{ |
|
void __iomem *mmio_base = ap->host->iomap[SIL_MMIO_BAR]; |
|
u32 tmp; |
|
|
|
/* clear IRQ */ |
|
ap->ops->sff_check_status(ap); |
|
ata_bmdma_irq_clear(ap); |
|
|
|
/* turn on SATA IRQ if supported */ |
|
if (!(ap->flags & SIL_FLAG_NO_SATA_IRQ)) |
|
writel(SIL_SIEN_N, mmio_base + sil_port[ap->port_no].sien); |
|
|
|
/* turn on IRQ */ |
|
tmp = readl(mmio_base + SIL_SYSCFG); |
|
tmp &= ~(SIL_MASK_IDE0_INT << ap->port_no); |
|
writel(tmp, mmio_base + SIL_SYSCFG); |
|
} |
|
|
|
/** |
|
* sil_dev_config - Apply device/host-specific errata fixups |
|
* @dev: Device to be examined |
|
* |
|
* After the IDENTIFY [PACKET] DEVICE step is complete, and a |
|
* device is known to be present, this function is called. |
|
* We apply two errata fixups which are specific to Silicon Image, |
|
* a Seagate and a Maxtor fixup. |
|
* |
|
* For certain Seagate devices, we must limit the maximum sectors |
|
* to under 8K. |
|
* |
|
* For certain Maxtor devices, we must not program the drive |
|
* beyond udma5. |
|
* |
|
* Both fixups are unfairly pessimistic. As soon as I get more |
|
* information on these errata, I will create a more exhaustive |
|
* list, and apply the fixups to only the specific |
|
* devices/hosts/firmwares that need it. |
|
* |
|
* 20040111 - Seagate drives affected by the Mod15Write bug are blacklisted |
|
* The Maxtor quirk is in the blacklist, but I'm keeping the original |
|
* pessimistic fix for the following reasons... |
|
* - There seems to be less info on it, only one device gleaned off the |
|
* Windows driver, maybe only one is affected. More info would be greatly |
|
* appreciated. |
|
* - But then again UDMA5 is hardly anything to complain about |
|
*/ |
|
static void sil_dev_config(struct ata_device *dev) |
|
{ |
|
struct ata_port *ap = dev->link->ap; |
|
int print_info = ap->link.eh_context.i.flags & ATA_EHI_PRINTINFO; |
|
unsigned int n, quirks = 0; |
|
unsigned char model_num[ATA_ID_PROD_LEN + 1]; |
|
|
|
/* This controller doesn't support trim */ |
|
dev->horkage |= ATA_HORKAGE_NOTRIM; |
|
|
|
ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num)); |
|
|
|
for (n = 0; sil_blacklist[n].product; n++) |
|
if (!strcmp(sil_blacklist[n].product, model_num)) { |
|
quirks = sil_blacklist[n].quirk; |
|
break; |
|
} |
|
|
|
/* limit requests to 15 sectors */ |
|
if (slow_down || |
|
((ap->flags & SIL_FLAG_MOD15WRITE) && |
|
(quirks & SIL_QUIRK_MOD15WRITE))) { |
|
if (print_info) |
|
ata_dev_info(dev, |
|
"applying Seagate errata fix (mod15write workaround)\n"); |
|
dev->max_sectors = 15; |
|
return; |
|
} |
|
|
|
/* limit to udma5 */ |
|
if (quirks & SIL_QUIRK_UDMA5MAX) { |
|
if (print_info) |
|
ata_dev_info(dev, "applying Maxtor errata fix %s\n", |
|
model_num); |
|
dev->udma_mask &= ATA_UDMA5; |
|
return; |
|
} |
|
} |
|
|
|
static void sil_init_controller(struct ata_host *host) |
|
{ |
|
struct pci_dev *pdev = to_pci_dev(host->dev); |
|
void __iomem *mmio_base = host->iomap[SIL_MMIO_BAR]; |
|
u8 cls; |
|
u32 tmp; |
|
int i; |
|
|
|
/* Initialize FIFO PCI bus arbitration */ |
|
cls = sil_get_device_cache_line(pdev); |
|
if (cls) { |
|
cls >>= 3; |
|
cls++; /* cls = (line_size/8)+1 */ |
|
for (i = 0; i < host->n_ports; i++) |
|
writew(cls << 8 | cls, |
|
mmio_base + sil_port[i].fifo_cfg); |
|
} else |
|
dev_warn(&pdev->dev, |
|
"cache line size not set. Driver may not function\n"); |
|
|
|
/* Apply R_ERR on DMA activate FIS errata workaround */ |
|
if (host->ports[0]->flags & SIL_FLAG_RERR_ON_DMA_ACT) { |
|
int cnt; |
|
|
|
for (i = 0, cnt = 0; i < host->n_ports; i++) { |
|
tmp = readl(mmio_base + sil_port[i].sfis_cfg); |
|
if ((tmp & 0x3) != 0x01) |
|
continue; |
|
if (!cnt) |
|
dev_info(&pdev->dev, |
|
"Applying R_ERR on DMA activate FIS errata fix\n"); |
|
writel(tmp & ~0x3, mmio_base + sil_port[i].sfis_cfg); |
|
cnt++; |
|
} |
|
} |
|
|
|
if (host->n_ports == 4) { |
|
/* flip the magic "make 4 ports work" bit */ |
|
tmp = readl(mmio_base + sil_port[2].bmdma); |
|
if ((tmp & SIL_INTR_STEERING) == 0) |
|
writel(tmp | SIL_INTR_STEERING, |
|
mmio_base + sil_port[2].bmdma); |
|
} |
|
} |
|
|
|
static bool sil_broken_system_poweroff(struct pci_dev *pdev) |
|
{ |
|
static const struct dmi_system_id broken_systems[] = { |
|
{ |
|
.ident = "HP Compaq nx6325", |
|
.matches = { |
|
DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), |
|
DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6325"), |
|
}, |
|
/* PCI slot number of the controller */ |
|
.driver_data = (void *)0x12UL, |
|
}, |
|
|
|
{ } /* terminate list */ |
|
}; |
|
const struct dmi_system_id *dmi = dmi_first_match(broken_systems); |
|
|
|
if (dmi) { |
|
unsigned long slot = (unsigned long)dmi->driver_data; |
|
/* apply the quirk only to on-board controllers */ |
|
return slot == PCI_SLOT(pdev->devfn); |
|
} |
|
|
|
return false; |
|
} |
|
|
|
static int sil_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
|
{ |
|
int board_id = ent->driver_data; |
|
struct ata_port_info pi = sil_port_info[board_id]; |
|
const struct ata_port_info *ppi[] = { &pi, NULL }; |
|
struct ata_host *host; |
|
void __iomem *mmio_base; |
|
int n_ports, rc; |
|
unsigned int i; |
|
|
|
ata_print_version_once(&pdev->dev, DRV_VERSION); |
|
|
|
/* allocate host */ |
|
n_ports = 2; |
|
if (board_id == sil_3114) |
|
n_ports = 4; |
|
|
|
if (sil_broken_system_poweroff(pdev)) { |
|
pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN | |
|
ATA_FLAG_NO_HIBERNATE_SPINDOWN; |
|
dev_info(&pdev->dev, "quirky BIOS, skipping spindown " |
|
"on poweroff and hibernation\n"); |
|
} |
|
|
|
host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
|
if (!host) |
|
return -ENOMEM; |
|
|
|
/* acquire resources and fill host */ |
|
rc = pcim_enable_device(pdev); |
|
if (rc) |
|
return rc; |
|
|
|
rc = pcim_iomap_regions(pdev, 1 << SIL_MMIO_BAR, DRV_NAME); |
|
if (rc == -EBUSY) |
|
pcim_pin_device(pdev); |
|
if (rc) |
|
return rc; |
|
host->iomap = pcim_iomap_table(pdev); |
|
|
|
rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); |
|
if (rc) |
|
return rc; |
|
|
|
mmio_base = host->iomap[SIL_MMIO_BAR]; |
|
|
|
for (i = 0; i < host->n_ports; i++) { |
|
struct ata_port *ap = host->ports[i]; |
|
struct ata_ioports *ioaddr = &ap->ioaddr; |
|
|
|
ioaddr->cmd_addr = mmio_base + sil_port[i].tf; |
|
ioaddr->altstatus_addr = |
|
ioaddr->ctl_addr = mmio_base + sil_port[i].ctl; |
|
ioaddr->bmdma_addr = mmio_base + sil_port[i].bmdma; |
|
ioaddr->scr_addr = mmio_base + sil_port[i].scr; |
|
ata_sff_std_ports(ioaddr); |
|
|
|
ata_port_pbar_desc(ap, SIL_MMIO_BAR, -1, "mmio"); |
|
ata_port_pbar_desc(ap, SIL_MMIO_BAR, sil_port[i].tf, "tf"); |
|
} |
|
|
|
/* initialize and activate */ |
|
sil_init_controller(host); |
|
|
|
pci_set_master(pdev); |
|
return ata_host_activate(host, pdev->irq, sil_interrupt, IRQF_SHARED, |
|
&sil_sht); |
|
} |
|
|
|
#ifdef CONFIG_PM_SLEEP |
|
static int sil_pci_device_resume(struct pci_dev *pdev) |
|
{ |
|
struct ata_host *host = pci_get_drvdata(pdev); |
|
int rc; |
|
|
|
rc = ata_pci_device_do_resume(pdev); |
|
if (rc) |
|
return rc; |
|
|
|
sil_init_controller(host); |
|
ata_host_resume(host); |
|
|
|
return 0; |
|
} |
|
#endif |
|
|
|
module_pci_driver(sil_pci_driver);
|
|
|