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304 lines
8.0 KiB
304 lines
8.0 KiB
// SPDX-License-Identifier: GPL-2.0-only |
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/* |
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* pata_efar.c - EFAR PIIX clone controller driver |
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* |
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* (C) 2005 Red Hat |
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* (C) 2009-2010 Bartlomiej Zolnierkiewicz |
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* |
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* Some parts based on ata_piix.c by Jeff Garzik and others. |
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* |
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* The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later |
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* Intel ICH controllers the EFAR widened the UDMA mode register bits |
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* and doesn't require the funky clock selection. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <scsi/scsi_host.h> |
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#include <linux/libata.h> |
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#include <linux/ata.h> |
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#define DRV_NAME "pata_efar" |
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#define DRV_VERSION "0.4.5" |
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/** |
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* efar_pre_reset - Enable bits |
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* @link: ATA link |
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* @deadline: deadline jiffies for the operation |
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* |
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* Perform cable detection for the EFAR ATA interface. This is |
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* different to the PIIX arrangement |
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*/ |
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static int efar_pre_reset(struct ata_link *link, unsigned long deadline) |
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{ |
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static const struct pci_bits efar_enable_bits[] = { |
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{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ |
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{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ |
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}; |
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struct ata_port *ap = link->ap; |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no])) |
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return -ENOENT; |
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return ata_sff_prereset(link, deadline); |
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} |
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/** |
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* efar_cable_detect - check for 40/80 pin |
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* @ap: Port |
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* |
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* Perform cable detection for the EFAR ATA interface. This is |
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* different to the PIIX arrangement |
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*/ |
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static int efar_cable_detect(struct ata_port *ap) |
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{ |
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struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
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u8 tmp; |
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pci_read_config_byte(pdev, 0x47, &tmp); |
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if (tmp & (2 >> ap->port_no)) |
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return ATA_CBL_PATA40; |
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return ATA_CBL_PATA80; |
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} |
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static DEFINE_SPINLOCK(efar_lock); |
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/** |
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* efar_set_piomode - Initialize host controller PATA PIO timings |
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* @ap: Port whose timings we are configuring |
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* @adev: Device to program |
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* |
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* Set PIO mode for device, in host controller PCI config space. |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev) |
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{ |
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unsigned int pio = adev->pio_mode - XFER_PIO_0; |
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struct pci_dev *dev = to_pci_dev(ap->host->dev); |
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unsigned int master_port = ap->port_no ? 0x42 : 0x40; |
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unsigned long flags; |
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u16 master_data; |
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u8 udma_enable; |
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int control = 0; |
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/* |
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* See Intel Document 298600-004 for the timing programing rules |
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* for PIIX/ICH. The EFAR is a clone so very similar |
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*/ |
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static const /* ISP RTC */ |
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u8 timings[][2] = { { 0, 0 }, |
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{ 0, 0 }, |
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{ 1, 0 }, |
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{ 2, 1 }, |
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{ 2, 3 }, }; |
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if (pio > 1) |
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control |= 1; /* TIME */ |
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if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */ |
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control |= 2; /* IE */ |
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/* Intel specifies that the prefetch/posting is for disk only */ |
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if (adev->class == ATA_DEV_ATA) |
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control |= 4; /* PPE */ |
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spin_lock_irqsave(&efar_lock, flags); |
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pci_read_config_word(dev, master_port, &master_data); |
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/* Set PPE, IE, and TIME as appropriate */ |
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if (adev->devno == 0) { |
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master_data &= 0xCCF0; |
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master_data |= control; |
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master_data |= (timings[pio][0] << 12) | |
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(timings[pio][1] << 8); |
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} else { |
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int shift = 4 * ap->port_no; |
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u8 slave_data; |
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master_data &= 0xFF0F; |
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master_data |= (control << 4); |
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/* Slave timing in separate register */ |
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pci_read_config_byte(dev, 0x44, &slave_data); |
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slave_data &= ap->port_no ? 0x0F : 0xF0; |
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift; |
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pci_write_config_byte(dev, 0x44, slave_data); |
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} |
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master_data |= 0x4000; /* Ensure SITRE is set */ |
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pci_write_config_word(dev, master_port, master_data); |
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pci_read_config_byte(dev, 0x48, &udma_enable); |
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udma_enable &= ~(1 << (2 * ap->port_no + adev->devno)); |
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pci_write_config_byte(dev, 0x48, udma_enable); |
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spin_unlock_irqrestore(&efar_lock, flags); |
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} |
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/** |
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* efar_set_dmamode - Initialize host controller PATA DMA timings |
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* @ap: Port whose timings we are configuring |
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* @adev: Device to program |
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* |
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* Set UDMA/MWDMA mode for device, in host controller PCI config space. |
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* |
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* LOCKING: |
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* None (inherited from caller). |
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*/ |
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static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev) |
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{ |
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struct pci_dev *dev = to_pci_dev(ap->host->dev); |
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u8 master_port = ap->port_no ? 0x42 : 0x40; |
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u16 master_data; |
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u8 speed = adev->dma_mode; |
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int devid = adev->devno + 2 * ap->port_no; |
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unsigned long flags; |
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u8 udma_enable; |
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static const /* ISP RTC */ |
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u8 timings[][2] = { { 0, 0 }, |
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{ 0, 0 }, |
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{ 1, 0 }, |
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{ 2, 1 }, |
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{ 2, 3 }, }; |
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spin_lock_irqsave(&efar_lock, flags); |
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pci_read_config_word(dev, master_port, &master_data); |
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pci_read_config_byte(dev, 0x48, &udma_enable); |
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if (speed >= XFER_UDMA_0) { |
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unsigned int udma = adev->dma_mode - XFER_UDMA_0; |
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u16 udma_timing; |
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udma_enable |= (1 << devid); |
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/* Load the UDMA mode number */ |
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pci_read_config_word(dev, 0x4A, &udma_timing); |
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udma_timing &= ~(7 << (4 * devid)); |
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udma_timing |= udma << (4 * devid); |
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pci_write_config_word(dev, 0x4A, udma_timing); |
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} else { |
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/* |
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* MWDMA is driven by the PIO timings. We must also enable |
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* IORDY unconditionally along with TIME1. PPE has already |
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* been set when the PIO timing was set. |
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*/ |
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unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; |
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unsigned int control; |
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u8 slave_data; |
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const unsigned int needed_pio[3] = { |
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XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 |
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}; |
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int pio = needed_pio[mwdma] - XFER_PIO_0; |
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control = 3; /* IORDY|TIME1 */ |
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/* If the drive MWDMA is faster than it can do PIO then |
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we must force PIO into PIO0 */ |
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if (adev->pio_mode < needed_pio[mwdma]) |
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/* Enable DMA timing only */ |
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control |= 8; /* PIO cycles in PIO0 */ |
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if (adev->devno) { /* Slave */ |
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master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ |
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master_data |= control << 4; |
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pci_read_config_byte(dev, 0x44, &slave_data); |
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slave_data &= ap->port_no ? 0x0F : 0xF0; |
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/* Load the matching timing */ |
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); |
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pci_write_config_byte(dev, 0x44, slave_data); |
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} else { /* Master */ |
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master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY |
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and master timing bits */ |
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master_data |= control; |
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master_data |= |
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(timings[pio][0] << 12) | |
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(timings[pio][1] << 8); |
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} |
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udma_enable &= ~(1 << devid); |
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pci_write_config_word(dev, master_port, master_data); |
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} |
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pci_write_config_byte(dev, 0x48, udma_enable); |
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spin_unlock_irqrestore(&efar_lock, flags); |
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} |
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static struct scsi_host_template efar_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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static struct ata_port_operations efar_ops = { |
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.inherits = &ata_bmdma_port_ops, |
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.cable_detect = efar_cable_detect, |
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.set_piomode = efar_set_piomode, |
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.set_dmamode = efar_set_dmamode, |
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.prereset = efar_pre_reset, |
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}; |
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/** |
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* efar_init_one - Register EFAR ATA PCI device with kernel services |
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* @pdev: PCI device to register |
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* @ent: Entry in efar_pci_tbl matching with @pdev |
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* |
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* Called from kernel PCI layer. |
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* |
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* LOCKING: |
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* Inherited from PCI layer (may sleep). |
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* |
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* RETURNS: |
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* Zero on success, or -ERRNO value. |
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*/ |
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static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
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{ |
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static const struct ata_port_info info = { |
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.flags = ATA_FLAG_SLAVE_POSS, |
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.pio_mask = ATA_PIO4, |
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.mwdma_mask = ATA_MWDMA12_ONLY, |
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.udma_mask = ATA_UDMA4, |
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.port_ops = &efar_ops, |
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}; |
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const struct ata_port_info *ppi[] = { &info, &info }; |
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ata_print_version_once(&pdev->dev, DRV_VERSION); |
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return ata_pci_bmdma_init_one(pdev, ppi, &efar_sht, NULL, |
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ATA_HOST_PARALLEL_SCAN); |
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} |
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static const struct pci_device_id efar_pci_tbl[] = { |
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{ PCI_VDEVICE(EFAR, 0x9130), }, |
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{ } /* terminate list */ |
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}; |
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static struct pci_driver efar_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = efar_pci_tbl, |
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.probe = efar_init_one, |
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.remove = ata_pci_remove_one, |
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#ifdef CONFIG_PM_SLEEP |
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.suspend = ata_pci_device_suspend, |
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.resume = ata_pci_device_resume, |
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#endif |
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}; |
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module_pci_driver(efar_pci_driver); |
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MODULE_AUTHOR("Alan Cox"); |
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MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, efar_pci_tbl); |
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MODULE_VERSION(DRV_VERSION);
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