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380 lines
10 KiB
380 lines
10 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Palmchip BK3710 PATA controller driver |
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* |
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* Copyright (c) 2017 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com |
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* |
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* Based on palm_bk3710.c: |
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* |
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* Copyright (C) 2006 Texas Instruments. |
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* Copyright (C) 2007 MontaVista Software, Inc., <[email protected]> |
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*/ |
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#include <linux/ata.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/ioport.h> |
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#include <linux/kernel.h> |
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#include <linux/libata.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/types.h> |
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#define DRV_NAME "pata_bk3710" |
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#define BK3710_TF_OFFSET 0x1F0 |
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#define BK3710_CTL_OFFSET 0x3F6 |
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#define BK3710_BMISP 0x02 |
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#define BK3710_IDETIMP 0x40 |
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#define BK3710_UDMACTL 0x48 |
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#define BK3710_MISCCTL 0x50 |
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#define BK3710_REGSTB 0x54 |
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#define BK3710_REGRCVR 0x58 |
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#define BK3710_DATSTB 0x5C |
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#define BK3710_DATRCVR 0x60 |
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#define BK3710_DMASTB 0x64 |
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#define BK3710_DMARCVR 0x68 |
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#define BK3710_UDMASTB 0x6C |
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#define BK3710_UDMATRP 0x70 |
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#define BK3710_UDMAENV 0x74 |
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#define BK3710_IORDYTMP 0x78 |
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static struct scsi_host_template pata_bk3710_sht = { |
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ATA_BMDMA_SHT(DRV_NAME), |
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}; |
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static unsigned int ideclk_period; /* in nanoseconds */ |
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struct pata_bk3710_udmatiming { |
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unsigned int rptime; /* tRP -- Ready to pause time (nsec) */ |
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unsigned int cycletime; /* tCYCTYP2/2 -- avg Cycle Time (nsec) */ |
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/* tENV is always a minimum of 20 nsec */ |
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}; |
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static const struct pata_bk3710_udmatiming pata_bk3710_udmatimings[6] = { |
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{ 160, 240 / 2 }, /* UDMA Mode 0 */ |
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{ 125, 160 / 2 }, /* UDMA Mode 1 */ |
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{ 100, 120 / 2 }, /* UDMA Mode 2 */ |
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{ 100, 90 / 2 }, /* UDMA Mode 3 */ |
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{ 100, 60 / 2 }, /* UDMA Mode 4 */ |
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{ 85, 40 / 2 }, /* UDMA Mode 5 */ |
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}; |
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static void pata_bk3710_setudmamode(void __iomem *base, unsigned int dev, |
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unsigned int mode) |
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{ |
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u32 val32; |
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u16 val16; |
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u8 tenv, trp, t0; |
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/* DMA Data Setup */ |
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t0 = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].cycletime, |
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ideclk_period) - 1; |
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tenv = DIV_ROUND_UP(20, ideclk_period) - 1; |
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trp = DIV_ROUND_UP(pata_bk3710_udmatimings[mode].rptime, |
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ideclk_period) - 1; |
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/* udmastb Ultra DMA Access Strobe Width */ |
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val32 = ioread32(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); |
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val32 |= t0 << (dev ? 8 : 0); |
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iowrite32(val32, base + BK3710_UDMASTB); |
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/* udmatrp Ultra DMA Ready to Pause Time */ |
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val32 = ioread32(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); |
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val32 |= trp << (dev ? 8 : 0); |
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iowrite32(val32, base + BK3710_UDMATRP); |
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/* udmaenv Ultra DMA envelop Time */ |
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val32 = ioread32(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); |
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val32 |= tenv << (dev ? 8 : 0); |
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iowrite32(val32, base + BK3710_UDMAENV); |
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/* Enable UDMA for Device */ |
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val16 = ioread16(base + BK3710_UDMACTL) | (1 << dev); |
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iowrite16(val16, base + BK3710_UDMACTL); |
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} |
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static void pata_bk3710_setmwdmamode(void __iomem *base, unsigned int dev, |
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unsigned short min_cycle, |
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unsigned int mode) |
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{ |
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const struct ata_timing *t; |
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int cycletime; |
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u32 val32; |
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u16 val16; |
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u8 td, tkw, t0; |
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t = ata_timing_find_mode(mode); |
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cycletime = max_t(int, t->cycle, min_cycle); |
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/* DMA Data Setup */ |
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t0 = DIV_ROUND_UP(cycletime, ideclk_period); |
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td = DIV_ROUND_UP(t->active, ideclk_period); |
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tkw = t0 - td - 1; |
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td--; |
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val32 = ioread32(base + BK3710_DMASTB) & (0xFF << (dev ? 0 : 8)); |
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val32 |= td << (dev ? 8 : 0); |
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iowrite32(val32, base + BK3710_DMASTB); |
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val32 = ioread32(base + BK3710_DMARCVR) & (0xFF << (dev ? 0 : 8)); |
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val32 |= tkw << (dev ? 8 : 0); |
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iowrite32(val32, base + BK3710_DMARCVR); |
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/* Disable UDMA for Device */ |
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val16 = ioread16(base + BK3710_UDMACTL) & ~(1 << dev); |
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iowrite16(val16, base + BK3710_UDMACTL); |
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} |
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static void pata_bk3710_set_dmamode(struct ata_port *ap, |
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struct ata_device *adev) |
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{ |
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void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr; |
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int is_slave = adev->devno; |
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const u8 xferspeed = adev->dma_mode; |
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if (xferspeed >= XFER_UDMA_0) |
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pata_bk3710_setudmamode(base, is_slave, |
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xferspeed - XFER_UDMA_0); |
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else |
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pata_bk3710_setmwdmamode(base, is_slave, |
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adev->id[ATA_ID_EIDE_DMA_MIN], |
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xferspeed); |
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} |
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static void pata_bk3710_setpiomode(void __iomem *base, struct ata_device *pair, |
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unsigned int dev, unsigned int cycletime, |
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unsigned int mode) |
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{ |
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const struct ata_timing *t; |
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u32 val32; |
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u8 t2, t2i, t0; |
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t = ata_timing_find_mode(XFER_PIO_0 + mode); |
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/* PIO Data Setup */ |
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t0 = DIV_ROUND_UP(cycletime, ideclk_period); |
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t2 = DIV_ROUND_UP(t->active, ideclk_period); |
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t2i = t0 - t2 - 1; |
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t2--; |
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val32 = ioread32(base + BK3710_DATSTB) & (0xFF << (dev ? 0 : 8)); |
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val32 |= t2 << (dev ? 8 : 0); |
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iowrite32(val32, base + BK3710_DATSTB); |
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val32 = ioread32(base + BK3710_DATRCVR) & (0xFF << (dev ? 0 : 8)); |
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val32 |= t2i << (dev ? 8 : 0); |
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iowrite32(val32, base + BK3710_DATRCVR); |
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/* FIXME: this is broken also in the old driver */ |
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if (pair) { |
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u8 mode2 = pair->pio_mode - XFER_PIO_0; |
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if (mode2 < mode) |
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mode = mode2; |
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} |
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/* TASKFILE Setup */ |
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t0 = DIV_ROUND_UP(t->cyc8b, ideclk_period); |
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t2 = DIV_ROUND_UP(t->act8b, ideclk_period); |
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t2i = t0 - t2 - 1; |
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t2--; |
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val32 = ioread32(base + BK3710_REGSTB) & (0xFF << (dev ? 0 : 8)); |
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val32 |= t2 << (dev ? 8 : 0); |
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iowrite32(val32, base + BK3710_REGSTB); |
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val32 = ioread32(base + BK3710_REGRCVR) & (0xFF << (dev ? 0 : 8)); |
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val32 |= t2i << (dev ? 8 : 0); |
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iowrite32(val32, base + BK3710_REGRCVR); |
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} |
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static void pata_bk3710_set_piomode(struct ata_port *ap, |
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struct ata_device *adev) |
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{ |
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void __iomem *base = (void __iomem *)ap->ioaddr.bmdma_addr; |
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struct ata_device *pair = ata_dev_pair(adev); |
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const struct ata_timing *t = ata_timing_find_mode(adev->pio_mode); |
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const u16 *id = adev->id; |
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unsigned int cycle_time = 0; |
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int is_slave = adev->devno; |
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const u8 pio = adev->pio_mode - XFER_PIO_0; |
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if (id[ATA_ID_FIELD_VALID] & 2) { |
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if (ata_id_has_iordy(id)) |
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cycle_time = id[ATA_ID_EIDE_PIO_IORDY]; |
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else |
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cycle_time = id[ATA_ID_EIDE_PIO]; |
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/* conservative "downgrade" for all pre-ATA2 drives */ |
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if (pio < 3 && cycle_time < t->cycle) |
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cycle_time = 0; /* use standard timing */ |
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} |
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if (!cycle_time) |
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cycle_time = t->cycle; |
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pata_bk3710_setpiomode(base, pair, is_slave, cycle_time, pio); |
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} |
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static void pata_bk3710_chipinit(void __iomem *base) |
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{ |
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/* |
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* REVISIT: the ATA reset signal needs to be managed through a |
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* GPIO, which means it should come from platform_data. Until |
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* we get and use such information, we have to trust that things |
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* have been reset before we get here. |
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*/ |
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/* |
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* Program the IDETIMP Register Value based on the following assumptions |
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* |
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* (ATA_IDETIMP_IDEEN , ENABLE ) | |
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* (ATA_IDETIMP_PREPOST1 , DISABLE) | |
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* (ATA_IDETIMP_PREPOST0 , DISABLE) | |
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* |
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* DM6446 silicon rev 2.1 and earlier have no observed net benefit |
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* from enabling prefetch/postwrite. |
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*/ |
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iowrite16(BIT(15), base + BK3710_IDETIMP); |
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/* |
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* UDMACTL Ultra-ATA DMA Control |
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* (ATA_UDMACTL_UDMAP1 , 0 ) | |
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* (ATA_UDMACTL_UDMAP0 , 0 ) |
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* |
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*/ |
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iowrite16(0, base + BK3710_UDMACTL); |
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/* |
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* MISCCTL Miscellaneous Conrol Register |
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* (ATA_MISCCTL_HWNHLD1P , 1 cycle) |
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* (ATA_MISCCTL_HWNHLD0P , 1 cycle) |
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* (ATA_MISCCTL_TIMORIDE , 1) |
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*/ |
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iowrite32(0x001, base + BK3710_MISCCTL); |
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/* |
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* IORDYTMP IORDY Timer for Primary Register |
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* (ATA_IORDYTMP_IORDYTMP , DISABLE) |
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*/ |
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iowrite32(0, base + BK3710_IORDYTMP); |
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/* |
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* Configure BMISP Register |
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* (ATA_BMISP_DMAEN1 , DISABLE ) | |
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* (ATA_BMISP_DMAEN0 , DISABLE ) | |
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* (ATA_BMISP_IORDYINT , CLEAR) | |
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* (ATA_BMISP_INTRSTAT , CLEAR) | |
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* (ATA_BMISP_DMAERROR , CLEAR) |
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*/ |
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iowrite16(0xE, base + BK3710_BMISP); |
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pata_bk3710_setpiomode(base, NULL, 0, 600, 0); |
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pata_bk3710_setpiomode(base, NULL, 1, 600, 0); |
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} |
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static struct ata_port_operations pata_bk3710_ports_ops = { |
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.inherits = &ata_bmdma_port_ops, |
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.cable_detect = ata_cable_80wire, |
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.set_piomode = pata_bk3710_set_piomode, |
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.set_dmamode = pata_bk3710_set_dmamode, |
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}; |
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static int __init pata_bk3710_probe(struct platform_device *pdev) |
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{ |
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struct clk *clk; |
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struct resource *mem; |
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struct ata_host *host; |
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struct ata_port *ap; |
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void __iomem *base; |
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unsigned long rate; |
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int irq; |
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clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(clk)) |
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return -ENODEV; |
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clk_enable(clk); |
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rate = clk_get_rate(clk); |
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if (!rate) |
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return -EINVAL; |
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/* NOTE: round *down* to meet minimum timings; we count in clocks */ |
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ideclk_period = 1000000000UL / rate; |
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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irq = platform_get_irq(pdev, 0); |
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if (irq < 0) { |
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pr_err(DRV_NAME ": failed to get IRQ resource\n"); |
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return irq; |
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} |
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base = devm_ioremap_resource(&pdev->dev, mem); |
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if (IS_ERR(base)) |
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return PTR_ERR(base); |
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/* configure the Palmchip controller */ |
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pata_bk3710_chipinit(base); |
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/* allocate host */ |
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host = ata_host_alloc(&pdev->dev, 1); |
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if (!host) |
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return -ENOMEM; |
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ap = host->ports[0]; |
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ap->ops = &pata_bk3710_ports_ops; |
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ap->pio_mask = ATA_PIO4; |
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ap->mwdma_mask = ATA_MWDMA2; |
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ap->udma_mask = rate < 100000000 ? ATA_UDMA4 : ATA_UDMA5; |
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ap->flags |= ATA_FLAG_SLAVE_POSS; |
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ap->ioaddr.data_addr = base + BK3710_TF_OFFSET; |
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ap->ioaddr.error_addr = base + BK3710_TF_OFFSET + 1; |
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ap->ioaddr.feature_addr = base + BK3710_TF_OFFSET + 1; |
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ap->ioaddr.nsect_addr = base + BK3710_TF_OFFSET + 2; |
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ap->ioaddr.lbal_addr = base + BK3710_TF_OFFSET + 3; |
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ap->ioaddr.lbam_addr = base + BK3710_TF_OFFSET + 4; |
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ap->ioaddr.lbah_addr = base + BK3710_TF_OFFSET + 5; |
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ap->ioaddr.device_addr = base + BK3710_TF_OFFSET + 6; |
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ap->ioaddr.status_addr = base + BK3710_TF_OFFSET + 7; |
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ap->ioaddr.command_addr = base + BK3710_TF_OFFSET + 7; |
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ap->ioaddr.altstatus_addr = base + BK3710_CTL_OFFSET; |
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ap->ioaddr.ctl_addr = base + BK3710_CTL_OFFSET; |
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ap->ioaddr.bmdma_addr = base; |
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ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", |
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(unsigned long)base + BK3710_TF_OFFSET, |
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(unsigned long)base + BK3710_CTL_OFFSET); |
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/* activate */ |
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return ata_host_activate(host, irq, ata_sff_interrupt, 0, |
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&pata_bk3710_sht); |
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} |
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/* work with hotplug and coldplug */ |
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MODULE_ALIAS("platform:palm_bk3710"); |
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static struct platform_driver pata_bk3710_driver = { |
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.driver = { |
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.name = "palm_bk3710", |
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}, |
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}; |
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static int __init pata_bk3710_init(void) |
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{ |
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return platform_driver_probe(&pata_bk3710_driver, pata_bk3710_probe); |
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} |
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module_init(pata_bk3710_init); |
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MODULE_LICENSE("GPL v2");
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