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467 lines
11 KiB
467 lines
11 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* acard-ahci.c - ACard AHCI SATA support |
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* |
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* Maintained by: Tejun Heo <[email protected]> |
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* Please ALWAYS copy [email protected] |
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* on emails. |
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* |
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* Copyright 2010 Red Hat, Inc. |
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* |
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* libata documentation is available via 'make {ps|pdf}docs', |
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* as Documentation/driver-api/libata.rst |
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* |
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* AHCI hardware documentation: |
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* http://www.intel.com/technology/serialata/pdf/rev1_0.pdf |
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* http://www.intel.com/technology/serialata/pdf/rev1_1.pdf |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/pci.h> |
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#include <linux/blkdev.h> |
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#include <linux/delay.h> |
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#include <linux/interrupt.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/device.h> |
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#include <linux/dmi.h> |
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#include <linux/gfp.h> |
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#include <scsi/scsi_host.h> |
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#include <scsi/scsi_cmnd.h> |
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#include <linux/libata.h> |
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#include "ahci.h" |
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#define DRV_NAME "acard-ahci" |
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#define DRV_VERSION "1.0" |
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/* |
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Received FIS structure limited to 80h. |
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*/ |
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#define ACARD_AHCI_RX_FIS_SZ 128 |
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enum { |
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AHCI_PCI_BAR = 5, |
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}; |
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enum board_ids { |
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board_acard_ahci, |
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}; |
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struct acard_sg { |
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__le32 addr; |
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__le32 addr_hi; |
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__le32 reserved; |
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__le32 size; /* bit 31 (EOT) max==0x10000 (64k) */ |
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}; |
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static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc); |
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static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc); |
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static int acard_ahci_port_start(struct ata_port *ap); |
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static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
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#ifdef CONFIG_PM_SLEEP |
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static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg); |
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static int acard_ahci_pci_device_resume(struct pci_dev *pdev); |
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#endif |
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static struct scsi_host_template acard_ahci_sht = { |
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AHCI_SHT("acard-ahci"), |
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}; |
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static struct ata_port_operations acard_ops = { |
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.inherits = &ahci_ops, |
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.qc_prep = acard_ahci_qc_prep, |
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.qc_fill_rtf = acard_ahci_qc_fill_rtf, |
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.port_start = acard_ahci_port_start, |
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}; |
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#define AHCI_HFLAGS(flags) .private_data = (void *)(flags) |
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static const struct ata_port_info acard_ahci_port_info[] = { |
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[board_acard_ahci] = |
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{ |
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AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ), |
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.flags = AHCI_FLAG_COMMON, |
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.pio_mask = ATA_PIO4, |
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.udma_mask = ATA_UDMA6, |
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.port_ops = &acard_ops, |
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}, |
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}; |
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static const struct pci_device_id acard_ahci_pci_tbl[] = { |
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/* ACard */ |
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{ PCI_VDEVICE(ARTOP, 0x000d), board_acard_ahci }, /* ATP8620 */ |
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{ } /* terminate list */ |
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}; |
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static struct pci_driver acard_ahci_pci_driver = { |
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.name = DRV_NAME, |
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.id_table = acard_ahci_pci_tbl, |
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.probe = acard_ahci_init_one, |
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.remove = ata_pci_remove_one, |
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#ifdef CONFIG_PM_SLEEP |
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.suspend = acard_ahci_pci_device_suspend, |
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.resume = acard_ahci_pci_device_resume, |
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#endif |
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}; |
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#ifdef CONFIG_PM_SLEEP |
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static int acard_ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg) |
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{ |
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struct ata_host *host = pci_get_drvdata(pdev); |
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struct ahci_host_priv *hpriv = host->private_data; |
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void __iomem *mmio = hpriv->mmio; |
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u32 ctl; |
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if (mesg.event & PM_EVENT_SUSPEND && |
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hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { |
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dev_err(&pdev->dev, |
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"BIOS update required for suspend/resume\n"); |
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return -EIO; |
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} |
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if (mesg.event & PM_EVENT_SLEEP) { |
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/* AHCI spec rev1.1 section 8.3.3: |
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* Software must disable interrupts prior to requesting a |
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* transition of the HBA to D3 state. |
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*/ |
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ctl = readl(mmio + HOST_CTL); |
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ctl &= ~HOST_IRQ_EN; |
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writel(ctl, mmio + HOST_CTL); |
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readl(mmio + HOST_CTL); /* flush */ |
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} |
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return ata_pci_device_suspend(pdev, mesg); |
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} |
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static int acard_ahci_pci_device_resume(struct pci_dev *pdev) |
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{ |
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struct ata_host *host = pci_get_drvdata(pdev); |
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int rc; |
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rc = ata_pci_device_do_resume(pdev); |
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if (rc) |
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return rc; |
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if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) { |
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rc = ahci_reset_controller(host); |
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if (rc) |
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return rc; |
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ahci_init_controller(host); |
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} |
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ata_host_resume(host); |
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return 0; |
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} |
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#endif |
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static void acard_ahci_pci_print_info(struct ata_host *host) |
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{ |
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struct pci_dev *pdev = to_pci_dev(host->dev); |
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u16 cc; |
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const char *scc_s; |
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pci_read_config_word(pdev, 0x0a, &cc); |
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if (cc == PCI_CLASS_STORAGE_IDE) |
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scc_s = "IDE"; |
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else if (cc == PCI_CLASS_STORAGE_SATA) |
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scc_s = "SATA"; |
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else if (cc == PCI_CLASS_STORAGE_RAID) |
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scc_s = "RAID"; |
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else |
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scc_s = "unknown"; |
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ahci_print_info(host, scc_s); |
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} |
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static unsigned int acard_ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl) |
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{ |
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struct scatterlist *sg; |
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struct acard_sg *acard_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ; |
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unsigned int si, last_si = 0; |
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VPRINTK("ENTER\n"); |
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/* |
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* Next, the S/G list. |
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*/ |
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for_each_sg(qc->sg, sg, qc->n_elem, si) { |
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dma_addr_t addr = sg_dma_address(sg); |
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u32 sg_len = sg_dma_len(sg); |
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/* |
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* ACard note: |
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* We must set an end-of-table (EOT) bit, |
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* and the segment cannot exceed 64k (0x10000) |
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*/ |
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acard_sg[si].addr = cpu_to_le32(addr & 0xffffffff); |
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acard_sg[si].addr_hi = cpu_to_le32((addr >> 16) >> 16); |
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acard_sg[si].size = cpu_to_le32(sg_len); |
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last_si = si; |
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} |
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acard_sg[last_si].size |= cpu_to_le32(1 << 31); /* set EOT */ |
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return si; |
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} |
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static enum ata_completion_errors acard_ahci_qc_prep(struct ata_queued_cmd *qc) |
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{ |
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struct ata_port *ap = qc->ap; |
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struct ahci_port_priv *pp = ap->private_data; |
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int is_atapi = ata_is_atapi(qc->tf.protocol); |
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void *cmd_tbl; |
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u32 opts; |
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const u32 cmd_fis_len = 5; /* five dwords */ |
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/* |
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* Fill in command table information. First, the header, |
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* a SATA Register - Host to Device command FIS. |
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*/ |
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cmd_tbl = pp->cmd_tbl + qc->hw_tag * AHCI_CMD_TBL_SZ; |
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ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, cmd_tbl); |
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if (is_atapi) { |
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memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32); |
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memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len); |
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} |
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if (qc->flags & ATA_QCFLAG_DMAMAP) |
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acard_ahci_fill_sg(qc, cmd_tbl); |
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/* |
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* Fill in command slot information. |
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* |
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* ACard note: prd table length not filled in |
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*/ |
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opts = cmd_fis_len | (qc->dev->link->pmp << 12); |
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if (qc->tf.flags & ATA_TFLAG_WRITE) |
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opts |= AHCI_CMD_WRITE; |
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if (is_atapi) |
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opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH; |
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ahci_fill_cmd_slot(pp, qc->hw_tag, opts); |
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return AC_ERR_OK; |
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} |
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static bool acard_ahci_qc_fill_rtf(struct ata_queued_cmd *qc) |
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{ |
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struct ahci_port_priv *pp = qc->ap->private_data; |
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u8 *rx_fis = pp->rx_fis; |
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if (pp->fbs_enabled) |
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rx_fis += qc->dev->link->pmp * ACARD_AHCI_RX_FIS_SZ; |
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/* |
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* After a successful execution of an ATA PIO data-in command, |
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* the device doesn't send D2H Reg FIS to update the TF and |
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* the host should take TF and E_Status from the preceding PIO |
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* Setup FIS. |
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*/ |
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if (qc->tf.protocol == ATA_PROT_PIO && qc->dma_dir == DMA_FROM_DEVICE && |
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!(qc->flags & ATA_QCFLAG_FAILED)) { |
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ata_tf_from_fis(rx_fis + RX_FIS_PIO_SETUP, &qc->result_tf); |
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qc->result_tf.command = (rx_fis + RX_FIS_PIO_SETUP)[15]; |
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} else |
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ata_tf_from_fis(rx_fis + RX_FIS_D2H_REG, &qc->result_tf); |
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return true; |
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} |
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static int acard_ahci_port_start(struct ata_port *ap) |
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{ |
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struct ahci_host_priv *hpriv = ap->host->private_data; |
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struct device *dev = ap->host->dev; |
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struct ahci_port_priv *pp; |
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void *mem; |
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dma_addr_t mem_dma; |
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size_t dma_sz, rx_fis_sz; |
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pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
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if (!pp) |
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return -ENOMEM; |
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/* check FBS capability */ |
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if ((hpriv->cap & HOST_CAP_FBS) && sata_pmp_supported(ap)) { |
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void __iomem *port_mmio = ahci_port_base(ap); |
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u32 cmd = readl(port_mmio + PORT_CMD); |
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if (cmd & PORT_CMD_FBSCP) |
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pp->fbs_supported = true; |
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else if (hpriv->flags & AHCI_HFLAG_YES_FBS) { |
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dev_info(dev, "port %d can do FBS, forcing FBSCP\n", |
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ap->port_no); |
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pp->fbs_supported = true; |
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} else |
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dev_warn(dev, "port %d is not capable of FBS\n", |
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ap->port_no); |
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} |
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if (pp->fbs_supported) { |
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dma_sz = AHCI_PORT_PRIV_FBS_DMA_SZ; |
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rx_fis_sz = ACARD_AHCI_RX_FIS_SZ * 16; |
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} else { |
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dma_sz = AHCI_PORT_PRIV_DMA_SZ; |
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rx_fis_sz = ACARD_AHCI_RX_FIS_SZ; |
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} |
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mem = dmam_alloc_coherent(dev, dma_sz, &mem_dma, GFP_KERNEL); |
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if (!mem) |
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return -ENOMEM; |
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/* |
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* First item in chunk of DMA memory: 32-slot command table, |
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* 32 bytes each in size |
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*/ |
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pp->cmd_slot = mem; |
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pp->cmd_slot_dma = mem_dma; |
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mem += AHCI_CMD_SLOT_SZ; |
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mem_dma += AHCI_CMD_SLOT_SZ; |
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/* |
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* Second item: Received-FIS area |
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*/ |
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pp->rx_fis = mem; |
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pp->rx_fis_dma = mem_dma; |
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mem += rx_fis_sz; |
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mem_dma += rx_fis_sz; |
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/* |
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* Third item: data area for storing a single command |
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* and its scatter-gather table |
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*/ |
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pp->cmd_tbl = mem; |
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pp->cmd_tbl_dma = mem_dma; |
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/* |
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* Save off initial list of interrupts to be enabled. |
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* This could be changed later |
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*/ |
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pp->intr_mask = DEF_PORT_IRQ; |
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ap->private_data = pp; |
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/* engage engines, captain */ |
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return ahci_port_resume(ap); |
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} |
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static int acard_ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
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{ |
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unsigned int board_id = ent->driver_data; |
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struct ata_port_info pi = acard_ahci_port_info[board_id]; |
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const struct ata_port_info *ppi[] = { &pi, NULL }; |
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struct device *dev = &pdev->dev; |
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struct ahci_host_priv *hpriv; |
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struct ata_host *host; |
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int n_ports, i, rc; |
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VPRINTK("ENTER\n"); |
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WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS); |
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ata_print_version_once(&pdev->dev, DRV_VERSION); |
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/* acquire resources */ |
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rc = pcim_enable_device(pdev); |
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if (rc) |
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return rc; |
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/* AHCI controllers often implement SFF compatible interface. |
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* Grab all PCI BARs just in case. |
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*/ |
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rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME); |
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if (rc == -EBUSY) |
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pcim_pin_device(pdev); |
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if (rc) |
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return rc; |
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hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL); |
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if (!hpriv) |
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return -ENOMEM; |
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hpriv->irq = pdev->irq; |
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hpriv->flags |= (unsigned long)pi.private_data; |
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if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) |
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pci_enable_msi(pdev); |
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hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR]; |
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/* save initial config */ |
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ahci_save_initial_config(&pdev->dev, hpriv); |
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/* prepare host */ |
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if (hpriv->cap & HOST_CAP_NCQ) |
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pi.flags |= ATA_FLAG_NCQ; |
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if (hpriv->cap & HOST_CAP_PMP) |
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pi.flags |= ATA_FLAG_PMP; |
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ahci_set_em_messages(hpriv, &pi); |
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/* CAP.NP sometimes indicate the index of the last enabled |
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* port, at other times, that of the last possible port, so |
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* determining the maximum port number requires looking at |
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* both CAP.NP and port_map. |
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*/ |
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n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map)); |
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host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
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if (!host) |
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return -ENOMEM; |
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host->private_data = hpriv; |
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if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss) |
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host->flags |= ATA_HOST_PARALLEL_SCAN; |
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else |
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printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n"); |
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for (i = 0; i < host->n_ports; i++) { |
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struct ata_port *ap = host->ports[i]; |
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ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar"); |
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ata_port_pbar_desc(ap, AHCI_PCI_BAR, |
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0x100 + ap->port_no * 0x80, "port"); |
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/* set initial link pm policy */ |
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/* |
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ap->pm_policy = NOT_AVAILABLE; |
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*/ |
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/* disabled/not-implemented port */ |
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if (!(hpriv->port_map & (1 << i))) |
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ap->ops = &ata_dummy_port_ops; |
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} |
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/* initialize adapter */ |
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rc = dma_set_mask_and_coherent(&pdev->dev, |
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DMA_BIT_MASK((hpriv->cap & HOST_CAP_64) ? 64 : 32)); |
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if (rc) { |
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dev_err(&pdev->dev, "DMA enable failed\n"); |
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return rc; |
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} |
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rc = ahci_reset_controller(host); |
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if (rc) |
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return rc; |
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ahci_init_controller(host); |
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acard_ahci_pci_print_info(host); |
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pci_set_master(pdev); |
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return ahci_host_activate(host, &acard_ahci_sht); |
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} |
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module_pci_driver(acard_ahci_pci_driver); |
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MODULE_AUTHOR("Jeff Garzik"); |
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MODULE_DESCRIPTION("ACard AHCI SATA low-level driver"); |
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MODULE_LICENSE("GPL"); |
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MODULE_DEVICE_TABLE(pci, acard_ahci_pci_tbl); |
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MODULE_VERSION(DRV_VERSION);
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