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601 lines
14 KiB
601 lines
14 KiB
// SPDX-License-Identifier: GPL-2.0-or-later |
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/* |
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* Driver for Digigram VXpocket soundcards |
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* |
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* lowlevel routines for VXpocket soundcards |
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* |
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* Copyright (c) 2002 by Takashi Iwai <[email protected]> |
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*/ |
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#include <linux/delay.h> |
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#include <linux/device.h> |
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#include <linux/firmware.h> |
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#include <linux/io.h> |
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#include <sound/core.h> |
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#include "vxpocket.h" |
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static const int vxp_reg_offset[VX_REG_MAX] = { |
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[VX_ICR] = 0x00, // ICR |
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[VX_CVR] = 0x01, // CVR |
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[VX_ISR] = 0x02, // ISR |
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[VX_IVR] = 0x03, // IVR |
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[VX_RXH] = 0x05, // RXH |
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[VX_RXM] = 0x06, // RXM |
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[VX_RXL] = 0x07, // RXL |
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[VX_DMA] = 0x04, // DMA |
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[VX_CDSP] = 0x08, // CDSP |
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[VX_LOFREQ] = 0x09, // LFREQ |
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[VX_HIFREQ] = 0x0a, // HFREQ |
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[VX_DATA] = 0x0b, // DATA |
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[VX_MICRO] = 0x0c, // MICRO |
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[VX_DIALOG] = 0x0d, // DIALOG |
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[VX_CSUER] = 0x0e, // CSUER |
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[VX_RUER] = 0x0f, // RUER |
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}; |
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static inline unsigned long vxp_reg_addr(struct vx_core *_chip, int reg) |
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{ |
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struct snd_vxpocket *chip = to_vxpocket(_chip); |
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return chip->port + vxp_reg_offset[reg]; |
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} |
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/* |
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* snd_vx_inb - read a byte from the register |
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* @offset: register offset |
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*/ |
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static unsigned char vxp_inb(struct vx_core *chip, int offset) |
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{ |
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return inb(vxp_reg_addr(chip, offset)); |
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} |
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/* |
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* snd_vx_outb - write a byte on the register |
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* @offset: the register offset |
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* @val: the value to write |
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*/ |
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static void vxp_outb(struct vx_core *chip, int offset, unsigned char val) |
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{ |
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outb(val, vxp_reg_addr(chip, offset)); |
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} |
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/* |
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* redefine macros to call directly |
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*/ |
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#undef vx_inb |
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#define vx_inb(chip,reg) vxp_inb((struct vx_core *)(chip), VX_##reg) |
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#undef vx_outb |
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#define vx_outb(chip,reg,val) vxp_outb((struct vx_core *)(chip), VX_##reg,val) |
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/* |
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* vx_check_magic - check the magic word on xilinx |
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* |
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* returns zero if a magic word is detected, or a negative error code. |
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*/ |
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static int vx_check_magic(struct vx_core *chip) |
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{ |
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unsigned long end_time = jiffies + HZ / 5; |
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int c; |
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do { |
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c = vx_inb(chip, CDSP); |
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if (c == CDSP_MAGIC) |
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return 0; |
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msleep(10); |
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} while (time_after_eq(end_time, jiffies)); |
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snd_printk(KERN_ERR "cannot find xilinx magic word (%x)\n", c); |
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return -EIO; |
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} |
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/* |
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* vx_reset_dsp - reset the DSP |
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*/ |
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#define XX_DSP_RESET_WAIT_TIME 2 /* ms */ |
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static void vxp_reset_dsp(struct vx_core *_chip) |
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{ |
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struct snd_vxpocket *chip = to_vxpocket(_chip); |
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/* set the reset dsp bit to 1 */ |
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vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_DSP_RESET_MASK); |
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vx_inb(chip, CDSP); |
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mdelay(XX_DSP_RESET_WAIT_TIME); |
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/* reset the bit */ |
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chip->regCDSP &= ~VXP_CDSP_DSP_RESET_MASK; |
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vx_outb(chip, CDSP, chip->regCDSP); |
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vx_inb(chip, CDSP); |
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mdelay(XX_DSP_RESET_WAIT_TIME); |
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} |
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/* |
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* reset codec bit |
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*/ |
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static void vxp_reset_codec(struct vx_core *_chip) |
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{ |
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struct snd_vxpocket *chip = to_vxpocket(_chip); |
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/* Set the reset CODEC bit to 1. */ |
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vx_outb(chip, CDSP, chip->regCDSP | VXP_CDSP_CODEC_RESET_MASK); |
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vx_inb(chip, CDSP); |
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msleep(10); |
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/* Set the reset CODEC bit to 0. */ |
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chip->regCDSP &= ~VXP_CDSP_CODEC_RESET_MASK; |
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vx_outb(chip, CDSP, chip->regCDSP); |
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vx_inb(chip, CDSP); |
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msleep(1); |
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} |
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/* |
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* vx_load_xilinx_binary - load the xilinx binary image |
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* the binary image is the binary array converted from the bitstream file. |
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*/ |
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static int vxp_load_xilinx_binary(struct vx_core *_chip, const struct firmware *fw) |
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{ |
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struct snd_vxpocket *chip = to_vxpocket(_chip); |
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unsigned int i; |
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int c; |
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int regCSUER, regRUER; |
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const unsigned char *image; |
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unsigned char data; |
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/* Switch to programmation mode */ |
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chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK; |
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vx_outb(chip, DIALOG, chip->regDIALOG); |
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/* Save register CSUER and RUER */ |
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regCSUER = vx_inb(chip, CSUER); |
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regRUER = vx_inb(chip, RUER); |
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/* reset HF0 and HF1 */ |
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vx_outb(chip, ICR, 0); |
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/* Wait for answer HF2 equal to 1 */ |
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snd_printdd(KERN_DEBUG "check ISR_HF2\n"); |
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if (vx_check_isr(_chip, ISR_HF2, ISR_HF2, 20) < 0) |
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goto _error; |
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/* set HF1 for loading xilinx binary */ |
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vx_outb(chip, ICR, ICR_HF1); |
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image = fw->data; |
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for (i = 0; i < fw->size; i++, image++) { |
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data = *image; |
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if (vx_wait_isr_bit(_chip, ISR_TX_EMPTY) < 0) |
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goto _error; |
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vx_outb(chip, TXL, data); |
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/* wait for reading */ |
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if (vx_wait_for_rx_full(_chip) < 0) |
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goto _error; |
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c = vx_inb(chip, RXL); |
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if (c != (int)data) |
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snd_printk(KERN_ERR "vxpocket: load xilinx mismatch at %d: 0x%x != 0x%x\n", i, c, (int)data); |
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} |
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/* reset HF1 */ |
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vx_outb(chip, ICR, 0); |
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/* wait for HF3 */ |
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if (vx_check_isr(_chip, ISR_HF3, ISR_HF3, 20) < 0) |
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goto _error; |
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/* read the number of bytes received */ |
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if (vx_wait_for_rx_full(_chip) < 0) |
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goto _error; |
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c = (int)vx_inb(chip, RXH) << 16; |
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c |= (int)vx_inb(chip, RXM) << 8; |
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c |= vx_inb(chip, RXL); |
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snd_printdd(KERN_DEBUG "xilinx: dsp size received 0x%x, orig 0x%zx\n", c, fw->size); |
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vx_outb(chip, ICR, ICR_HF0); |
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/* TEMPO 250ms : wait until Xilinx is downloaded */ |
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msleep(300); |
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/* test magical word */ |
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if (vx_check_magic(_chip) < 0) |
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goto _error; |
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/* Restore register 0x0E and 0x0F (thus replacing COR and FCSR) */ |
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vx_outb(chip, CSUER, regCSUER); |
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vx_outb(chip, RUER, regRUER); |
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/* Reset the Xilinx's signal enabling IO access */ |
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chip->regDIALOG |= VXP_DLG_XILINX_REPROG_MASK; |
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vx_outb(chip, DIALOG, chip->regDIALOG); |
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vx_inb(chip, DIALOG); |
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msleep(10); |
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chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK; |
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vx_outb(chip, DIALOG, chip->regDIALOG); |
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vx_inb(chip, DIALOG); |
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/* Reset of the Codec */ |
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vxp_reset_codec(_chip); |
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vx_reset_dsp(_chip); |
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return 0; |
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_error: |
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vx_outb(chip, CSUER, regCSUER); |
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vx_outb(chip, RUER, regRUER); |
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chip->regDIALOG &= ~VXP_DLG_XILINX_REPROG_MASK; |
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vx_outb(chip, DIALOG, chip->regDIALOG); |
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return -EIO; |
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} |
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/* |
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* vxp_load_dsp - load_dsp callback |
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*/ |
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static int vxp_load_dsp(struct vx_core *vx, int index, const struct firmware *fw) |
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{ |
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int err; |
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switch (index) { |
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case 0: |
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/* xilinx boot */ |
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err = vx_check_magic(vx); |
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if (err < 0) |
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return err; |
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err = snd_vx_load_boot_image(vx, fw); |
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if (err < 0) |
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return err; |
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return 0; |
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case 1: |
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/* xilinx image */ |
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return vxp_load_xilinx_binary(vx, fw); |
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case 2: |
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/* DSP boot */ |
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return snd_vx_dsp_boot(vx, fw); |
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case 3: |
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/* DSP image */ |
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return snd_vx_dsp_load(vx, fw); |
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default: |
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snd_BUG(); |
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return -EINVAL; |
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} |
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} |
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/* |
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* vx_test_and_ack - test and acknowledge interrupt |
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* |
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* called from irq hander, too |
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* |
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* spinlock held! |
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*/ |
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static int vxp_test_and_ack(struct vx_core *_chip) |
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{ |
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struct snd_vxpocket *chip = to_vxpocket(_chip); |
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/* not booted yet? */ |
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if (! (_chip->chip_status & VX_STAT_XILINX_LOADED)) |
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return -ENXIO; |
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if (! (vx_inb(chip, DIALOG) & VXP_DLG_MEMIRQ_MASK)) |
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return -EIO; |
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/* ok, interrupts generated, now ack it */ |
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/* set ACQUIT bit up and down */ |
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vx_outb(chip, DIALOG, chip->regDIALOG | VXP_DLG_ACK_MEMIRQ_MASK); |
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/* useless read just to spend some time and maintain |
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* the ACQUIT signal up for a while ( a bus cycle ) |
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*/ |
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vx_inb(chip, DIALOG); |
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vx_outb(chip, DIALOG, chip->regDIALOG & ~VXP_DLG_ACK_MEMIRQ_MASK); |
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return 0; |
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} |
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/* |
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* vx_validate_irq - enable/disable IRQ |
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*/ |
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static void vxp_validate_irq(struct vx_core *_chip, int enable) |
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{ |
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struct snd_vxpocket *chip = to_vxpocket(_chip); |
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/* Set the interrupt enable bit to 1 in CDSP register */ |
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if (enable) |
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chip->regCDSP |= VXP_CDSP_VALID_IRQ_MASK; |
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else |
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chip->regCDSP &= ~VXP_CDSP_VALID_IRQ_MASK; |
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vx_outb(chip, CDSP, chip->regCDSP); |
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} |
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/* |
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* vx_setup_pseudo_dma - set up the pseudo dma read/write mode. |
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* @do_write: 0 = read, 1 = set up for DMA write |
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*/ |
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static void vx_setup_pseudo_dma(struct vx_core *_chip, int do_write) |
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{ |
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struct snd_vxpocket *chip = to_vxpocket(_chip); |
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/* Interrupt mode and HREQ pin enabled for host transmit / receive data transfers */ |
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vx_outb(chip, ICR, do_write ? ICR_TREQ : ICR_RREQ); |
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/* Reset the pseudo-dma register */ |
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vx_inb(chip, ISR); |
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vx_outb(chip, ISR, 0); |
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/* Select DMA in read/write transfer mode and in 16-bit accesses */ |
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chip->regDIALOG |= VXP_DLG_DMA16_SEL_MASK; |
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chip->regDIALOG |= do_write ? VXP_DLG_DMAWRITE_SEL_MASK : VXP_DLG_DMAREAD_SEL_MASK; |
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vx_outb(chip, DIALOG, chip->regDIALOG); |
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} |
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/* |
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* vx_release_pseudo_dma - disable the pseudo-DMA mode |
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*/ |
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static void vx_release_pseudo_dma(struct vx_core *_chip) |
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{ |
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struct snd_vxpocket *chip = to_vxpocket(_chip); |
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/* Disable DMA and 16-bit accesses */ |
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chip->regDIALOG &= ~(VXP_DLG_DMAWRITE_SEL_MASK| |
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VXP_DLG_DMAREAD_SEL_MASK| |
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VXP_DLG_DMA16_SEL_MASK); |
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vx_outb(chip, DIALOG, chip->regDIALOG); |
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/* HREQ pin disabled. */ |
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vx_outb(chip, ICR, 0); |
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} |
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/* |
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* vx_pseudo_dma_write - write bulk data on pseudo-DMA mode |
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* @count: data length to transfer in bytes |
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* |
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* data size must be aligned to 6 bytes to ensure the 24bit alignment on DSP. |
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* NB: call with a certain lock! |
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*/ |
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static void vxp_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime, |
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struct vx_pipe *pipe, int count) |
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{ |
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long port = vxp_reg_addr(chip, VX_DMA); |
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int offset = pipe->hw_ptr; |
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unsigned short *addr = (unsigned short *)(runtime->dma_area + offset); |
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vx_setup_pseudo_dma(chip, 1); |
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if (offset + count >= pipe->buffer_bytes) { |
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int length = pipe->buffer_bytes - offset; |
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count -= length; |
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length >>= 1; /* in 16bit words */ |
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/* Transfer using pseudo-dma. */ |
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for (; length > 0; length--) { |
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outw(*addr, port); |
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addr++; |
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} |
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addr = (unsigned short *)runtime->dma_area; |
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pipe->hw_ptr = 0; |
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} |
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pipe->hw_ptr += count; |
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count >>= 1; /* in 16bit words */ |
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/* Transfer using pseudo-dma. */ |
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for (; count > 0; count--) { |
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outw(*addr, port); |
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addr++; |
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} |
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vx_release_pseudo_dma(chip); |
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} |
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/* |
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* vx_pseudo_dma_read - read bulk data on pseudo DMA mode |
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* @offset: buffer offset in bytes |
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* @count: data length to transfer in bytes |
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* |
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* the read length must be aligned to 6 bytes, as well as write. |
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* NB: call with a certain lock! |
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*/ |
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static void vxp_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime, |
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struct vx_pipe *pipe, int count) |
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{ |
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struct snd_vxpocket *pchip = to_vxpocket(chip); |
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long port = vxp_reg_addr(chip, VX_DMA); |
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int offset = pipe->hw_ptr; |
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unsigned short *addr = (unsigned short *)(runtime->dma_area + offset); |
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if (snd_BUG_ON(count % 2)) |
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return; |
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vx_setup_pseudo_dma(chip, 0); |
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if (offset + count >= pipe->buffer_bytes) { |
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int length = pipe->buffer_bytes - offset; |
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count -= length; |
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length >>= 1; /* in 16bit words */ |
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/* Transfer using pseudo-dma. */ |
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for (; length > 0; length--) |
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*addr++ = inw(port); |
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addr = (unsigned short *)runtime->dma_area; |
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pipe->hw_ptr = 0; |
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} |
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pipe->hw_ptr += count; |
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count >>= 1; /* in 16bit words */ |
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/* Transfer using pseudo-dma. */ |
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for (; count > 1; count--) |
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*addr++ = inw(port); |
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/* Disable DMA */ |
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pchip->regDIALOG &= ~VXP_DLG_DMAREAD_SEL_MASK; |
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vx_outb(chip, DIALOG, pchip->regDIALOG); |
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/* Read the last word (16 bits) */ |
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*addr = inw(port); |
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/* Disable 16-bit accesses */ |
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pchip->regDIALOG &= ~VXP_DLG_DMA16_SEL_MASK; |
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vx_outb(chip, DIALOG, pchip->regDIALOG); |
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/* HREQ pin disabled. */ |
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vx_outb(chip, ICR, 0); |
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} |
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/* |
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* write a codec data (24bit) |
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*/ |
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static void vxp_write_codec_reg(struct vx_core *chip, int codec, unsigned int data) |
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{ |
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int i; |
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/* Activate access to the corresponding codec register */ |
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if (! codec) |
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vx_inb(chip, LOFREQ); |
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else |
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vx_inb(chip, CODEC2); |
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/* We have to send 24 bits (3 x 8 bits). Start with most signif. Bit */ |
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for (i = 0; i < 24; i++, data <<= 1) |
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vx_outb(chip, DATA, ((data & 0x800000) ? VX_DATA_CODEC_MASK : 0)); |
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/* Terminate access to codec registers */ |
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vx_inb(chip, HIFREQ); |
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} |
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/* |
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* vx_set_mic_boost - set mic boost level (on vxp440 only) |
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* @boost: 0 = 20dB, 1 = +38dB |
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*/ |
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void vx_set_mic_boost(struct vx_core *chip, int boost) |
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{ |
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struct snd_vxpocket *pchip = to_vxpocket(chip); |
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if (chip->chip_status & VX_STAT_IS_STALE) |
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return; |
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mutex_lock(&chip->lock); |
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if (pchip->regCDSP & P24_CDSP_MICS_SEL_MASK) { |
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if (boost) { |
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/* boost: 38 dB */ |
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pchip->regCDSP &= ~P24_CDSP_MIC20_SEL_MASK; |
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pchip->regCDSP |= P24_CDSP_MIC38_SEL_MASK; |
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} else { |
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/* minimum value: 20 dB */ |
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pchip->regCDSP |= P24_CDSP_MIC20_SEL_MASK; |
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pchip->regCDSP &= ~P24_CDSP_MIC38_SEL_MASK; |
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} |
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vx_outb(chip, CDSP, pchip->regCDSP); |
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} |
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mutex_unlock(&chip->lock); |
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} |
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/* |
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* remap the linear value (0-8) to the actual value (0-15) |
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*/ |
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static int vx_compute_mic_level(int level) |
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{ |
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switch (level) { |
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case 5: level = 6 ; break; |
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case 6: level = 8 ; break; |
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case 7: level = 11; break; |
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case 8: level = 15; break; |
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default: break ; |
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} |
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return level; |
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} |
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/* |
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* vx_set_mic_level - set mic level (on vxpocket only) |
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* @level: the mic level = 0 - 8 (max) |
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*/ |
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void vx_set_mic_level(struct vx_core *chip, int level) |
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{ |
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struct snd_vxpocket *pchip = to_vxpocket(chip); |
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if (chip->chip_status & VX_STAT_IS_STALE) |
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return; |
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mutex_lock(&chip->lock); |
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if (pchip->regCDSP & VXP_CDSP_MIC_SEL_MASK) { |
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level = vx_compute_mic_level(level); |
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vx_outb(chip, MICRO, level); |
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} |
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mutex_unlock(&chip->lock); |
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} |
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/* |
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* change the input audio source |
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*/ |
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static void vxp_change_audio_source(struct vx_core *_chip, int src) |
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{ |
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struct snd_vxpocket *chip = to_vxpocket(_chip); |
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switch (src) { |
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case VX_AUDIO_SRC_DIGITAL: |
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chip->regCDSP |= VXP_CDSP_DATAIN_SEL_MASK; |
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vx_outb(chip, CDSP, chip->regCDSP); |
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break; |
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case VX_AUDIO_SRC_LINE: |
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chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK; |
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if (_chip->type == VX_TYPE_VXP440) |
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chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK; |
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else |
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chip->regCDSP &= ~VXP_CDSP_MIC_SEL_MASK; |
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vx_outb(chip, CDSP, chip->regCDSP); |
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break; |
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case VX_AUDIO_SRC_MIC: |
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chip->regCDSP &= ~VXP_CDSP_DATAIN_SEL_MASK; |
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/* reset mic levels */ |
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if (_chip->type == VX_TYPE_VXP440) { |
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chip->regCDSP &= ~P24_CDSP_MICS_SEL_MASK; |
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if (chip->mic_level) |
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chip->regCDSP |= P24_CDSP_MIC38_SEL_MASK; |
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else |
|
chip->regCDSP |= P24_CDSP_MIC20_SEL_MASK; |
|
vx_outb(chip, CDSP, chip->regCDSP); |
|
} else { |
|
chip->regCDSP |= VXP_CDSP_MIC_SEL_MASK; |
|
vx_outb(chip, CDSP, chip->regCDSP); |
|
vx_outb(chip, MICRO, vx_compute_mic_level(chip->mic_level)); |
|
} |
|
break; |
|
} |
|
} |
|
|
|
/* |
|
* change the clock source |
|
* source = INTERNAL_QUARTZ or UER_SYNC |
|
*/ |
|
static void vxp_set_clock_source(struct vx_core *_chip, int source) |
|
{ |
|
struct snd_vxpocket *chip = to_vxpocket(_chip); |
|
|
|
if (source == INTERNAL_QUARTZ) |
|
chip->regCDSP &= ~VXP_CDSP_CLOCKIN_SEL_MASK; |
|
else |
|
chip->regCDSP |= VXP_CDSP_CLOCKIN_SEL_MASK; |
|
vx_outb(chip, CDSP, chip->regCDSP); |
|
} |
|
|
|
|
|
/* |
|
* reset the board |
|
*/ |
|
static void vxp_reset_board(struct vx_core *_chip, int cold_reset) |
|
{ |
|
struct snd_vxpocket *chip = to_vxpocket(_chip); |
|
|
|
chip->regCDSP = 0; |
|
chip->regDIALOG = 0; |
|
} |
|
|
|
|
|
/* |
|
* callbacks |
|
*/ |
|
/* exported */ |
|
const struct snd_vx_ops snd_vxpocket_ops = { |
|
.in8 = vxp_inb, |
|
.out8 = vxp_outb, |
|
.test_and_ack = vxp_test_and_ack, |
|
.validate_irq = vxp_validate_irq, |
|
.write_codec = vxp_write_codec_reg, |
|
.reset_codec = vxp_reset_codec, |
|
.change_audio_source = vxp_change_audio_source, |
|
.set_clock_source = vxp_set_clock_source, |
|
.load_dsp = vxp_load_dsp, |
|
.add_controls = vxp_add_mic_controls, |
|
.reset_dsp = vxp_reset_dsp, |
|
.reset_board = vxp_reset_board, |
|
.dma_write = vxp_dma_write, |
|
.dma_read = vxp_dma_read, |
|
};
|
|
|