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155 lines
2.7 KiB
155 lines
2.7 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* (C) Copyright 2002 |
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* Wolfgang Denk, DENX Software Engineering, [email protected]. |
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*/ |
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#include <common.h> |
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/* |
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* CPU test |
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* Binary instructions instr rD,rA |
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* |
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* Logic instructions: neg |
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* Arithmetic instructions: addme, addze, subfme, subfze |
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* The test contains a pre-built table of instructions, operands and |
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* expected results. For each table entry, the test will cyclically use |
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* different sets of operand registers and result registers. |
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*/ |
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#include <post.h> |
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#include "cpu_asm.h" |
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#if CONFIG_POST & CONFIG_SYS_POST_CPU |
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extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); |
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extern ulong cpu_post_makecr (long v); |
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static struct cpu_post_two_s |
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{ |
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ulong cmd; |
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ulong op; |
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ulong res; |
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} cpu_post_two_table[] = |
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{ |
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{ |
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OP_NEG, |
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3, |
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-3 |
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}, |
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{ |
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OP_NEG, |
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5, |
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-5 |
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}, |
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{ |
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OP_ADDME, |
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6, |
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5 |
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}, |
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{ |
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OP_ADDZE, |
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5, |
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5 |
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}, |
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{ |
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OP_SUBFME, |
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6, |
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~6 - 1 |
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}, |
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{ |
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OP_SUBFZE, |
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5, |
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~5 |
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}, |
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}; |
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static unsigned int cpu_post_two_size = ARRAY_SIZE(cpu_post_two_table); |
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int cpu_post_test_two (void) |
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{ |
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int ret = 0; |
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unsigned int i, reg; |
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int flag = disable_interrupts(); |
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for (i = 0; i < cpu_post_two_size && ret == 0; i++) |
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{ |
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struct cpu_post_two_s *test = cpu_post_two_table + i; |
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for (reg = 0; reg < 32 && ret == 0; reg++) |
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{ |
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unsigned int reg0 = (reg + 0) % 32; |
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unsigned int reg1 = (reg + 1) % 32; |
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unsigned int stk = reg < 16 ? 31 : 15; |
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unsigned long code[] = |
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{ |
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ASM_STW(stk, 1, -4), |
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ASM_ADDI(stk, 1, -16), |
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ASM_STW(3, stk, 8), |
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ASM_STW(reg0, stk, 4), |
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ASM_STW(reg1, stk, 0), |
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ASM_LWZ(reg0, stk, 8), |
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ASM_11(test->cmd, reg1, reg0), |
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ASM_STW(reg1, stk, 8), |
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ASM_LWZ(reg1, stk, 0), |
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ASM_LWZ(reg0, stk, 4), |
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ASM_LWZ(3, stk, 8), |
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ASM_ADDI(1, stk, 16), |
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ASM_LWZ(stk, 1, -4), |
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ASM_BLR, |
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}; |
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unsigned long codecr[] = |
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{ |
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ASM_STW(stk, 1, -4), |
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ASM_ADDI(stk, 1, -16), |
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ASM_STW(3, stk, 8), |
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ASM_STW(reg0, stk, 4), |
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ASM_STW(reg1, stk, 0), |
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ASM_LWZ(reg0, stk, 8), |
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ASM_11(test->cmd, reg1, reg0) | BIT_C, |
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ASM_STW(reg1, stk, 8), |
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ASM_LWZ(reg1, stk, 0), |
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ASM_LWZ(reg0, stk, 4), |
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ASM_LWZ(3, stk, 8), |
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ASM_ADDI(1, stk, 16), |
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ASM_LWZ(stk, 1, -4), |
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ASM_BLR, |
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}; |
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ulong res; |
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ulong cr; |
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if (ret == 0) |
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{ |
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cr = 0; |
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cpu_post_exec_21 (code, & cr, & res, test->op); |
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ret = res == test->res && cr == 0 ? 0 : -1; |
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if (ret != 0) |
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{ |
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post_log ("Error at two test %d !\n", i); |
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} |
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} |
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if (ret == 0) |
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{ |
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cpu_post_exec_21 (codecr, & cr, & res, test->op); |
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ret = res == test->res && |
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(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; |
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if (ret != 0) |
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{ |
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post_log ("Error at two test %d !\n", i); |
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} |
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} |
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} |
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} |
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if (flag) |
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enable_interrupts(); |
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return ret; |
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} |
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#endif
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