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236 lines
5.8 KiB
236 lines
5.8 KiB
// SPDX-License-Identifier: GPL-2.0+ |
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/* |
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* Copyright (C) 2012 Michal Simek <[email protected]> |
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* Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. |
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*/ |
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#include <clk.h> |
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#include <common.h> |
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#include <debug_uart.h> |
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#include <dm.h> |
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#include <errno.h> |
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#include <fdtdec.h> |
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#include <watchdog.h> |
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#include <asm/io.h> |
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#include <linux/compiler.h> |
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#include <serial.h> |
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DECLARE_GLOBAL_DATA_PTR; |
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#define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ |
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#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ |
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#define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ |
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#define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */ |
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#define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */ |
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#define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */ |
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#define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */ |
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#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ |
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struct uart_zynq { |
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u32 control; /* 0x0 - Control Register [8:0] */ |
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u32 mode; /* 0x4 - Mode Register [10:0] */ |
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u32 reserved1[4]; |
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u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */ |
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u32 reserved2[4]; |
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u32 channel_sts; /* 0x2c - Channel Status [11:0] */ |
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u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */ |
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u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ |
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}; |
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struct zynq_uart_platdata { |
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struct uart_zynq *regs; |
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}; |
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/* Set up the baud rate in gd struct */ |
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static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, |
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unsigned long clock, unsigned long baud) |
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{ |
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/* Calculation results. */ |
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unsigned int calc_bauderror, bdiv, bgen; |
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unsigned long calc_baud = 0; |
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/* Covering case where input clock is so slow */ |
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if (clock < 1000000 && baud > 4800) |
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baud = 4800; |
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/* master clock |
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* Baud rate = ------------------ |
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* bgen * (bdiv + 1) |
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* |
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* Find acceptable values for baud generation. |
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*/ |
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for (bdiv = 4; bdiv < 255; bdiv++) { |
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bgen = clock / (baud * (bdiv + 1)); |
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if (bgen < 2 || bgen > 65535) |
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continue; |
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calc_baud = clock / (bgen * (bdiv + 1)); |
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/* |
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* Use first calculated baudrate with |
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* an acceptable (<3%) error |
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*/ |
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if (baud > calc_baud) |
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calc_bauderror = baud - calc_baud; |
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else |
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calc_bauderror = calc_baud - baud; |
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if (((calc_bauderror * 100) / baud) < 3) |
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break; |
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} |
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writel(bdiv, ®s->baud_rate_divider); |
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writel(bgen, ®s->baud_rate_gen); |
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} |
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/* Initialize the UART, with...some settings. */ |
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static void _uart_zynq_serial_init(struct uart_zynq *regs) |
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{ |
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/* RX/TX enabled & reset */ |
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writel(ZYNQ_UART_CR_TX_EN | ZYNQ_UART_CR_RX_EN | ZYNQ_UART_CR_TXRST | \ |
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ZYNQ_UART_CR_RXRST, ®s->control); |
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writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ |
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} |
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static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) |
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{ |
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if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) |
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return -EAGAIN; |
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writel(c, ®s->tx_rx_fifo); |
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return 0; |
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} |
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static int zynq_serial_setbrg(struct udevice *dev, int baudrate) |
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{ |
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struct zynq_uart_platdata *platdata = dev_get_platdata(dev); |
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unsigned long clock; |
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int ret; |
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struct clk clk; |
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ret = clk_get_by_index(dev, 0, &clk); |
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if (ret < 0) { |
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dev_err(dev, "failed to get clock\n"); |
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return ret; |
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} |
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clock = clk_get_rate(&clk); |
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if (IS_ERR_VALUE(clock)) { |
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dev_err(dev, "failed to get rate\n"); |
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return clock; |
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} |
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debug("%s: CLK %ld\n", __func__, clock); |
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ret = clk_enable(&clk); |
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if (ret && ret != -ENOSYS) { |
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dev_err(dev, "failed to enable clock\n"); |
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return ret; |
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} |
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_uart_zynq_serial_setbrg(platdata->regs, clock, baudrate); |
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return 0; |
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} |
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static int zynq_serial_probe(struct udevice *dev) |
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{ |
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struct zynq_uart_platdata *platdata = dev_get_platdata(dev); |
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/* No need to reinitialize the UART after relocation */ |
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if (gd->flags & GD_FLG_RELOC) |
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return 0; |
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_uart_zynq_serial_init(platdata->regs); |
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return 0; |
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} |
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static int zynq_serial_getc(struct udevice *dev) |
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{ |
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struct zynq_uart_platdata *platdata = dev_get_platdata(dev); |
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struct uart_zynq *regs = platdata->regs; |
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if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) |
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return -EAGAIN; |
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return readl(®s->tx_rx_fifo); |
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} |
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static int zynq_serial_putc(struct udevice *dev, const char ch) |
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{ |
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struct zynq_uart_platdata *platdata = dev_get_platdata(dev); |
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return _uart_zynq_serial_putc(platdata->regs, ch); |
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} |
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static int zynq_serial_pending(struct udevice *dev, bool input) |
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{ |
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struct zynq_uart_platdata *platdata = dev_get_platdata(dev); |
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struct uart_zynq *regs = platdata->regs; |
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if (input) |
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return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); |
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else |
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return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); |
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} |
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static int zynq_serial_ofdata_to_platdata(struct udevice *dev) |
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{ |
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struct zynq_uart_platdata *platdata = dev_get_platdata(dev); |
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platdata->regs = (struct uart_zynq *)dev_read_addr(dev); |
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if (IS_ERR(platdata->regs)) |
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return PTR_ERR(platdata->regs); |
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return 0; |
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} |
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static const struct dm_serial_ops zynq_serial_ops = { |
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.putc = zynq_serial_putc, |
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.pending = zynq_serial_pending, |
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.getc = zynq_serial_getc, |
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.setbrg = zynq_serial_setbrg, |
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}; |
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static const struct udevice_id zynq_serial_ids[] = { |
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{ .compatible = "xlnx,xuartps" }, |
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{ .compatible = "cdns,uart-r1p8" }, |
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{ .compatible = "cdns,uart-r1p12" }, |
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{ } |
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}; |
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U_BOOT_DRIVER(serial_zynq) = { |
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.name = "serial_zynq", |
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.id = UCLASS_SERIAL, |
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.of_match = zynq_serial_ids, |
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.ofdata_to_platdata = zynq_serial_ofdata_to_platdata, |
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.platdata_auto_alloc_size = sizeof(struct zynq_uart_platdata), |
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.probe = zynq_serial_probe, |
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.ops = &zynq_serial_ops, |
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.flags = DM_FLAG_PRE_RELOC, |
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}; |
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#ifdef CONFIG_DEBUG_UART_ZYNQ |
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static inline void _debug_uart_init(void) |
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{ |
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struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; |
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_uart_zynq_serial_init(regs); |
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_uart_zynq_serial_setbrg(regs, CONFIG_DEBUG_UART_CLOCK, |
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CONFIG_BAUDRATE); |
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} |
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static inline void _debug_uart_putc(int ch) |
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{ |
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struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE; |
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while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN) |
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WATCHDOG_RESET(); |
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} |
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DEBUG_UART_FUNCS |
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#endif
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