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184 lines
5.8 KiB
184 lines
5.8 KiB
/* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (c) 2005 Silicon Graphics, Inc. All Rights Reserved. |
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*/ |
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#ifndef _LINUX_IOC4_H |
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#define _LINUX_IOC4_H |
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#include <linux/interrupt.h> |
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/*************** |
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* Definitions * |
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***************/ |
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/* Miscellaneous values inherent to hardware */ |
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#define IOC4_EXTINT_COUNT_DIVISOR 520 /* PCI clocks per COUNT tick */ |
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/*********************************** |
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* Structures needed by subdrivers * |
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***********************************/ |
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/* This structure fully describes the IOC4 miscellaneous registers which |
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* appear at bar[0]+0x00000 through bar[0]+0x0005c. The corresponding |
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* PCI resource is managed by the main IOC4 driver because it contains |
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* registers of interest to many different IOC4 subdrivers. |
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*/ |
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struct ioc4_misc_regs { |
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/* Miscellaneous IOC4 registers */ |
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union ioc4_pci_err_addr_l { |
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uint32_t raw; |
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struct { |
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uint32_t valid:1; /* Address captured */ |
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uint32_t master_id:4; /* Unit causing error |
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* 0/1: Serial port 0 TX/RX |
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* 2/3: Serial port 1 TX/RX |
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* 4/5: Serial port 2 TX/RX |
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* 6/7: Serial port 3 TX/RX |
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* 8: ATA/ATAPI |
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* 9-15: Undefined |
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*/ |
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uint32_t mul_err:1; /* Multiple errors occurred */ |
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uint32_t addr:26; /* Bits 31-6 of error addr */ |
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} fields; |
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} pci_err_addr_l; |
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uint32_t pci_err_addr_h; /* Bits 63-32 of error addr */ |
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union ioc4_sio_int { |
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uint32_t raw; |
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struct { |
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uint8_t tx_mt:1; /* TX ring buffer empty */ |
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uint8_t rx_full:1; /* RX ring buffer full */ |
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uint8_t rx_high:1; /* RX high-water exceeded */ |
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uint8_t rx_timer:1; /* RX timer has triggered */ |
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uint8_t delta_dcd:1; /* DELTA_DCD seen */ |
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uint8_t delta_cts:1; /* DELTA_CTS seen */ |
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uint8_t intr_pass:1; /* Interrupt pass-through */ |
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uint8_t tx_explicit:1; /* TX, MCW, or delay complete */ |
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} fields[4]; |
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} sio_ir; /* Serial interrupt state */ |
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union ioc4_other_int { |
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uint32_t raw; |
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struct { |
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uint32_t ata_int:1; /* ATA port passthru */ |
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uint32_t ata_memerr:1; /* ATA halted by mem error */ |
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uint32_t memerr:4; /* Serial halted by mem err */ |
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uint32_t kbd_int:1; /* kbd/mouse intr asserted */ |
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uint32_t reserved:16; /* zero */ |
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uint32_t rt_int:1; /* INT_OUT section latch */ |
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uint32_t gen_int:8; /* Intr. from generic pins */ |
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} fields; |
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} other_ir; /* Other interrupt state */ |
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union ioc4_sio_int sio_ies; /* Serial interrupt enable set */ |
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union ioc4_other_int other_ies; /* Other interrupt enable set */ |
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union ioc4_sio_int sio_iec; /* Serial interrupt enable clear */ |
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union ioc4_other_int other_iec; /* Other interrupt enable clear */ |
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union ioc4_sio_cr { |
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uint32_t raw; |
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struct { |
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uint32_t cmd_pulse:4; /* Bytebus strobe width */ |
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uint32_t arb_diag:3; /* PCI bus requester */ |
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uint32_t sio_diag_idle:1; /* Active ser req? */ |
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uint32_t ata_diag_idle:1; /* Active ATA req? */ |
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uint32_t ata_diag_active:1; /* ATA req is winner */ |
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uint32_t reserved:22; /* zero */ |
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} fields; |
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} sio_cr; |
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uint32_t unused1; |
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union ioc4_int_out { |
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uint32_t raw; |
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struct { |
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uint32_t count:16; /* Period control */ |
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uint32_t mode:3; /* Output signal shape */ |
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uint32_t reserved:11; /* zero */ |
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uint32_t diag:1; /* Timebase control */ |
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uint32_t int_out:1; /* Current value */ |
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} fields; |
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} int_out; /* External interrupt output control */ |
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uint32_t unused2; |
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union ioc4_gpcr { |
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uint32_t raw; |
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struct { |
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uint32_t dir:8; /* Pin direction */ |
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uint32_t edge:8; /* Edge/level mode */ |
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uint32_t reserved1:4; /* zero */ |
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uint32_t int_out_en:1; /* INT_OUT enable */ |
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uint32_t reserved2:11; /* zero */ |
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} fields; |
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} gpcr_s; /* Generic PIO control set */ |
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union ioc4_gpcr gpcr_c; /* Generic PIO control clear */ |
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union ioc4_gpdr { |
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uint32_t raw; |
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struct { |
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uint32_t gen_pin:8; /* State of pins */ |
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uint32_t reserved:24; |
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} fields; |
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} gpdr; /* Generic PIO data */ |
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uint32_t unused3; |
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union ioc4_gppr { |
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uint32_t raw; |
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struct { |
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uint32_t gen_pin:1; /* Single pin state */ |
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uint32_t reserved:31; |
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} fields; |
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} gppr[8]; /* Generic PIO pins */ |
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}; |
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/* Masks for GPCR DIR pins */ |
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#define IOC4_GPCR_DIR_0 0x01 /* External interrupt output */ |
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#define IOC4_GPCR_DIR_1 0x02 /* External interrupt input */ |
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#define IOC4_GPCR_DIR_2 0x04 |
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#define IOC4_GPCR_DIR_3 0x08 /* Keyboard/mouse presence */ |
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#define IOC4_GPCR_DIR_4 0x10 /* Ser. port 0 xcvr select (0=232, 1=422) */ |
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#define IOC4_GPCR_DIR_5 0x20 /* Ser. port 1 xcvr select (0=232, 1=422) */ |
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#define IOC4_GPCR_DIR_6 0x40 /* Ser. port 2 xcvr select (0=232, 1=422) */ |
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#define IOC4_GPCR_DIR_7 0x80 /* Ser. port 3 xcvr select (0=232, 1=422) */ |
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/* Masks for GPCR EDGE pins */ |
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#define IOC4_GPCR_EDGE_0 0x01 |
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#define IOC4_GPCR_EDGE_1 0x02 /* External interrupt input */ |
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#define IOC4_GPCR_EDGE_2 0x04 |
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#define IOC4_GPCR_EDGE_3 0x08 |
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#define IOC4_GPCR_EDGE_4 0x10 |
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#define IOC4_GPCR_EDGE_5 0x20 |
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#define IOC4_GPCR_EDGE_6 0x40 |
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#define IOC4_GPCR_EDGE_7 0x80 |
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#define IOC4_VARIANT_IO9 0x0900 |
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#define IOC4_VARIANT_PCI_RT 0x0901 |
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#define IOC4_VARIANT_IO10 0x1000 |
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/* One of these per IOC4 */ |
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struct ioc4_driver_data { |
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struct list_head idd_list; |
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unsigned long idd_bar0; |
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struct pci_dev *idd_pdev; |
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const struct pci_device_id *idd_pci_id; |
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struct ioc4_misc_regs __iomem *idd_misc_regs; |
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unsigned long count_period; |
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void *idd_serial_data; |
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unsigned int idd_variant; |
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}; |
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/* One per submodule */ |
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struct ioc4_submodule { |
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struct list_head is_list; |
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char *is_name; |
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struct module *is_owner; |
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int (*is_probe) (struct ioc4_driver_data *); |
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int (*is_remove) (struct ioc4_driver_data *); |
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}; |
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#define IOC4_NUM_CARDS 8 /* max cards per partition */ |
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/********************************** |
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* Functions needed by submodules * |
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**********************************/ |
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extern int ioc4_register_submodule(struct ioc4_submodule *); |
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extern void ioc4_unregister_submodule(struct ioc4_submodule *); |
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#endif /* _LINUX_IOC4_H */
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