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42 lines
1.3 KiB
42 lines
1.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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/* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved. */ |
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/* |
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* This header provides constants for the nvidia,tegra241-gpio DT binding. |
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* |
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* The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below |
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* provide names for this. |
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* |
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* The second cell contains standard flag values specified in gpio.h. |
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*/ |
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#ifndef _DT_BINDINGS_GPIO_TEGRA241_GPIO_H |
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#define _DT_BINDINGS_GPIO_TEGRA241_GPIO_H |
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#include <dt-bindings/gpio/gpio.h> |
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/* GPIOs implemented by main GPIO controller */ |
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#define TEGRA241_MAIN_GPIO_PORT_A 0 |
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#define TEGRA241_MAIN_GPIO_PORT_B 1 |
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#define TEGRA241_MAIN_GPIO_PORT_C 2 |
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#define TEGRA241_MAIN_GPIO_PORT_D 3 |
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#define TEGRA241_MAIN_GPIO_PORT_E 4 |
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#define TEGRA241_MAIN_GPIO_PORT_F 5 |
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#define TEGRA241_MAIN_GPIO_PORT_G 6 |
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#define TEGRA241_MAIN_GPIO_PORT_H 7 |
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#define TEGRA241_MAIN_GPIO_PORT_I 8 |
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#define TEGRA241_MAIN_GPIO_PORT_J 9 |
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#define TEGRA241_MAIN_GPIO_PORT_K 10 |
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#define TEGRA241_MAIN_GPIO_PORT_L 11 |
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#define TEGRA241_MAIN_GPIO(port, offset) \ |
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((TEGRA241_MAIN_GPIO_PORT_##port * 8) + (offset)) |
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/* GPIOs implemented by AON GPIO controller */ |
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#define TEGRA241_AON_GPIO_PORT_AA 0 |
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#define TEGRA241_AON_GPIO_PORT_BB 1 |
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#define TEGRA241_AON_GPIO(port, offset) \ |
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((TEGRA241_AON_GPIO_PORT_##port * 8) + (offset)) |
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#endif
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