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698 lines
19 KiB
698 lines
19 KiB
/* |
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* linux/arch/arm/mach-omap1/pm.c |
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* |
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* OMAP Power Management Routines |
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* |
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* Original code for the SA11x0: |
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* Copyright (c) 2001 Cliff Brake <[email protected]> |
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* |
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* Modified for the PXA250 by Nicolas Pitre: |
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* Copyright (c) 2002 Monta Vista Software, Inc. |
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* |
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* Modified for the OMAP1510 by David Singleton: |
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* Copyright (c) 2002 Monta Vista Software, Inc. |
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* |
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* Cleanup 2004 for OMAP1510/1610 by Dirk Behme <[email protected]> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* You should have received a copy of the GNU General Public License along |
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* with this program; if not, write to the Free Software Foundation, Inc., |
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* 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <linux/suspend.h> |
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#include <linux/sched.h> |
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#include <linux/debugfs.h> |
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#include <linux/seq_file.h> |
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#include <linux/interrupt.h> |
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#include <linux/sysfs.h> |
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#include <linux/module.h> |
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#include <linux/io.h> |
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#include <linux/atomic.h> |
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#include <linux/cpu.h> |
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#include <asm/fncpy.h> |
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#include <asm/system_misc.h> |
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#include <asm/irq.h> |
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#include <asm/mach/time.h> |
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#include <asm/mach/irq.h> |
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#include <linux/soc/ti/omap1-io.h> |
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#include "tc.h" |
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#include <linux/omap-dma.h> |
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#include <clocksource/timer-ti-dm.h> |
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#include "hardware.h" |
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#include "mux.h" |
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#include "irqs.h" |
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#include "iomap.h" |
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#include "clock.h" |
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#include "pm.h" |
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#include "soc.h" |
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#include "sram.h" |
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static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE]; |
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static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE]; |
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static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE]; |
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static unsigned int mpui7xx_sleep_save[MPUI7XX_SLEEP_SAVE_SIZE]; |
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static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE]; |
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static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE]; |
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static unsigned short enable_dyn_sleep; |
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static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr, |
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char *buf) |
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{ |
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return sprintf(buf, "%hu\n", enable_dyn_sleep); |
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} |
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static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr, |
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const char * buf, size_t n) |
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{ |
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unsigned short value; |
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if (sscanf(buf, "%hu", &value) != 1 || |
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(value != 0 && value != 1) || |
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(value != 0 && !IS_ENABLED(CONFIG_OMAP_32K_TIMER))) { |
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pr_err("idle_sleep_store: Invalid value\n"); |
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return -EINVAL; |
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} |
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enable_dyn_sleep = value; |
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return n; |
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} |
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static struct kobj_attribute sleep_while_idle_attr = |
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__ATTR(sleep_while_idle, 0644, idle_show, idle_store); |
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static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL; |
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/* |
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* Let's power down on idle, but only if we are really |
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* idle, because once we start down the path of |
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* going idle we continue to do idle even if we get |
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* a clock tick interrupt . . |
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*/ |
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void omap1_pm_idle(void) |
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{ |
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extern __u32 arm_idlect1_mask; |
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__u32 use_idlect1 = arm_idlect1_mask; |
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local_fiq_disable(); |
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#if defined(CONFIG_OMAP_MPU_TIMER) && !defined(CONFIG_OMAP_DM_TIMER) |
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use_idlect1 = use_idlect1 & ~(1 << 9); |
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#endif |
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#ifdef CONFIG_OMAP_DM_TIMER |
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use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1); |
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#endif |
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if (omap_dma_running()) |
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use_idlect1 &= ~(1 << 6); |
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/* |
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* We should be able to remove the do_sleep variable and multiple |
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* tests above as soon as drivers, timer and DMA code have been fixed. |
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* Even the sleep block count should become obsolete. |
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*/ |
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if ((use_idlect1 != ~0) || !enable_dyn_sleep) { |
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__u32 saved_idlect1 = omap_readl(ARM_IDLECT1); |
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if (cpu_is_omap15xx()) |
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use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST; |
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else |
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use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL; |
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omap_writel(use_idlect1, ARM_IDLECT1); |
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__asm__ volatile ("mcr p15, 0, r0, c7, c0, 4"); |
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omap_writel(saved_idlect1, ARM_IDLECT1); |
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local_fiq_enable(); |
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return; |
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} |
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omap_sram_suspend(omap_readl(ARM_IDLECT1), |
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omap_readl(ARM_IDLECT2)); |
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local_fiq_enable(); |
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} |
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/* |
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* Configuration of the wakeup event is board specific. For the |
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* moment we put it into this helper function. Later it may move |
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* to board specific files. |
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*/ |
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static void omap_pm_wakeup_setup(void) |
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{ |
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u32 level1_wake = 0; |
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u32 level2_wake = OMAP_IRQ_BIT(INT_UART2); |
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/* |
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* Turn off all interrupts except GPIO bank 1, L1-2nd level cascade, |
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* and the L2 wakeup interrupts: keypad and UART2. Note that the |
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* drivers must still separately call omap_set_gpio_wakeup() to |
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* wake up to a GPIO interrupt. |
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*/ |
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if (cpu_is_omap7xx()) |
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level1_wake = OMAP_IRQ_BIT(INT_7XX_GPIO_BANK1) | |
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OMAP_IRQ_BIT(INT_7XX_IH2_IRQ); |
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else if (cpu_is_omap15xx()) |
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level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | |
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OMAP_IRQ_BIT(INT_1510_IH2_IRQ); |
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else if (cpu_is_omap16xx()) |
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level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) | |
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OMAP_IRQ_BIT(INT_1610_IH2_IRQ); |
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omap_writel(~level1_wake, OMAP_IH1_MIR); |
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if (cpu_is_omap7xx()) { |
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omap_writel(~level2_wake, OMAP_IH2_0_MIR); |
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omap_writel(~(OMAP_IRQ_BIT(INT_7XX_WAKE_UP_REQ) | |
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OMAP_IRQ_BIT(INT_7XX_MPUIO_KEYPAD)), |
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OMAP_IH2_1_MIR); |
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} else if (cpu_is_omap15xx()) { |
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level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); |
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omap_writel(~level2_wake, OMAP_IH2_MIR); |
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} else if (cpu_is_omap16xx()) { |
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level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD); |
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omap_writel(~level2_wake, OMAP_IH2_0_MIR); |
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/* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */ |
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omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ), |
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OMAP_IH2_1_MIR); |
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omap_writel(~0x0, OMAP_IH2_2_MIR); |
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omap_writel(~0x0, OMAP_IH2_3_MIR); |
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} |
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/* New IRQ agreement, recalculate in cascade order */ |
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omap_writel(1, OMAP_IH2_CONTROL); |
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omap_writel(1, OMAP_IH1_CONTROL); |
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} |
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#define EN_DSPCK 13 /* ARM_CKCTL */ |
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#define EN_APICK 6 /* ARM_IDLECT2 */ |
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#define DSP_EN 1 /* ARM_RSTCT1 */ |
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void omap1_pm_suspend(void) |
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{ |
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unsigned long arg0 = 0, arg1 = 0; |
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printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n", |
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omap_rev()); |
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omap_serial_wake_trigger(1); |
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if (!cpu_is_omap15xx()) |
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omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG); |
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/* |
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* Step 1: turn off interrupts (FIXME: NOTE: already disabled) |
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*/ |
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local_irq_disable(); |
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local_fiq_disable(); |
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/* |
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* Step 2: save registers |
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* |
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* The omap is a strange/beautiful device. The caches, memory |
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* and register state are preserved across power saves. |
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* We have to save and restore very little register state to |
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* idle the omap. |
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* |
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* Save interrupt, MPUI, ARM and UPLD control registers. |
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*/ |
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if (cpu_is_omap7xx()) { |
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MPUI7XX_SAVE(OMAP_IH1_MIR); |
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MPUI7XX_SAVE(OMAP_IH2_0_MIR); |
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MPUI7XX_SAVE(OMAP_IH2_1_MIR); |
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MPUI7XX_SAVE(MPUI_CTRL); |
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MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); |
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MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); |
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MPUI7XX_SAVE(EMIFS_CONFIG); |
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MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); |
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} else if (cpu_is_omap15xx()) { |
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MPUI1510_SAVE(OMAP_IH1_MIR); |
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MPUI1510_SAVE(OMAP_IH2_MIR); |
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MPUI1510_SAVE(MPUI_CTRL); |
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MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); |
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MPUI1510_SAVE(MPUI_DSP_API_CONFIG); |
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MPUI1510_SAVE(EMIFS_CONFIG); |
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MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); |
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} else if (cpu_is_omap16xx()) { |
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MPUI1610_SAVE(OMAP_IH1_MIR); |
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MPUI1610_SAVE(OMAP_IH2_0_MIR); |
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MPUI1610_SAVE(OMAP_IH2_1_MIR); |
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MPUI1610_SAVE(OMAP_IH2_2_MIR); |
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MPUI1610_SAVE(OMAP_IH2_3_MIR); |
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MPUI1610_SAVE(MPUI_CTRL); |
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MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); |
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MPUI1610_SAVE(MPUI_DSP_API_CONFIG); |
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MPUI1610_SAVE(EMIFS_CONFIG); |
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MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); |
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} |
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ARM_SAVE(ARM_CKCTL); |
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ARM_SAVE(ARM_IDLECT1); |
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ARM_SAVE(ARM_IDLECT2); |
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if (!(cpu_is_omap15xx())) |
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ARM_SAVE(ARM_IDLECT3); |
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ARM_SAVE(ARM_EWUPCT); |
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ARM_SAVE(ARM_RSTCT1); |
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ARM_SAVE(ARM_RSTCT2); |
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ARM_SAVE(ARM_SYSST); |
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ULPD_SAVE(ULPD_CLOCK_CTRL); |
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ULPD_SAVE(ULPD_STATUS_REQ); |
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/* (Step 3 removed - we now allow deep sleep by default) */ |
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/* |
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* Step 4: OMAP DSP Shutdown |
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*/ |
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/* stop DSP */ |
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omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1); |
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/* shut down dsp_ck */ |
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if (!cpu_is_omap7xx()) |
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omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); |
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/* temporarily enabling api_ck to access DSP registers */ |
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omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); |
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/* save DSP registers */ |
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DSP_SAVE(DSP_IDLECT2); |
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/* Stop all DSP domain clocks */ |
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__raw_writew(0, DSP_IDLECT2); |
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/* |
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* Step 5: Wakeup Event Setup |
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*/ |
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omap_pm_wakeup_setup(); |
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/* |
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* Step 6: ARM and Traffic controller shutdown |
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*/ |
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/* disable ARM watchdog */ |
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omap_writel(0x00F5, OMAP_WDT_TIMER_MODE); |
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omap_writel(0x00A0, OMAP_WDT_TIMER_MODE); |
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/* |
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* Step 6b: ARM and Traffic controller shutdown |
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* |
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* Step 6 continues here. Prepare jump to power management |
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* assembly code in internal SRAM. |
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* |
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* Since the omap_cpu_suspend routine has been copied to |
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* SRAM, we'll do an indirect procedure call to it and pass the |
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* contents of arm_idlect1 and arm_idlect2 so it can restore |
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* them when it wakes up and it will return. |
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*/ |
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arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1]; |
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arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2]; |
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/* |
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* Step 6c: ARM and Traffic controller shutdown |
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* |
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* Jump to assembly code. The processor will stay there |
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* until wake up. |
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*/ |
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omap_sram_suspend(arg0, arg1); |
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/* |
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* If we are here, processor is woken up! |
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*/ |
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/* |
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* Restore DSP clocks |
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*/ |
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/* again temporarily enabling api_ck to access DSP registers */ |
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omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2); |
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/* Restore DSP domain clocks */ |
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DSP_RESTORE(DSP_IDLECT2); |
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/* |
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* Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did |
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*/ |
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if (!(cpu_is_omap15xx())) |
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ARM_RESTORE(ARM_IDLECT3); |
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ARM_RESTORE(ARM_CKCTL); |
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ARM_RESTORE(ARM_EWUPCT); |
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ARM_RESTORE(ARM_RSTCT1); |
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ARM_RESTORE(ARM_RSTCT2); |
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ARM_RESTORE(ARM_SYSST); |
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ULPD_RESTORE(ULPD_CLOCK_CTRL); |
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ULPD_RESTORE(ULPD_STATUS_REQ); |
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if (cpu_is_omap7xx()) { |
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MPUI7XX_RESTORE(EMIFS_CONFIG); |
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MPUI7XX_RESTORE(EMIFF_SDRAM_CONFIG); |
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MPUI7XX_RESTORE(OMAP_IH1_MIR); |
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MPUI7XX_RESTORE(OMAP_IH2_0_MIR); |
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MPUI7XX_RESTORE(OMAP_IH2_1_MIR); |
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} else if (cpu_is_omap15xx()) { |
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MPUI1510_RESTORE(MPUI_CTRL); |
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MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG); |
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MPUI1510_RESTORE(MPUI_DSP_API_CONFIG); |
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MPUI1510_RESTORE(EMIFS_CONFIG); |
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MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG); |
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MPUI1510_RESTORE(OMAP_IH1_MIR); |
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MPUI1510_RESTORE(OMAP_IH2_MIR); |
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} else if (cpu_is_omap16xx()) { |
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MPUI1610_RESTORE(MPUI_CTRL); |
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MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG); |
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MPUI1610_RESTORE(MPUI_DSP_API_CONFIG); |
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MPUI1610_RESTORE(EMIFS_CONFIG); |
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MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG); |
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MPUI1610_RESTORE(OMAP_IH1_MIR); |
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MPUI1610_RESTORE(OMAP_IH2_0_MIR); |
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MPUI1610_RESTORE(OMAP_IH2_1_MIR); |
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MPUI1610_RESTORE(OMAP_IH2_2_MIR); |
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MPUI1610_RESTORE(OMAP_IH2_3_MIR); |
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} |
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if (!cpu_is_omap15xx()) |
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omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG); |
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/* |
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* Re-enable interrupts |
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*/ |
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local_irq_enable(); |
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local_fiq_enable(); |
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omap_serial_wake_trigger(0); |
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printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n", |
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omap_rev()); |
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} |
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#ifdef CONFIG_DEBUG_FS |
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/* |
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* Read system PM registers for debugging |
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*/ |
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static int omap_pm_debug_show(struct seq_file *m, void *v) |
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{ |
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ARM_SAVE(ARM_CKCTL); |
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ARM_SAVE(ARM_IDLECT1); |
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ARM_SAVE(ARM_IDLECT2); |
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if (!(cpu_is_omap15xx())) |
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ARM_SAVE(ARM_IDLECT3); |
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ARM_SAVE(ARM_EWUPCT); |
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ARM_SAVE(ARM_RSTCT1); |
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ARM_SAVE(ARM_RSTCT2); |
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ARM_SAVE(ARM_SYSST); |
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|
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ULPD_SAVE(ULPD_IT_STATUS); |
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ULPD_SAVE(ULPD_CLOCK_CTRL); |
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ULPD_SAVE(ULPD_SOFT_REQ); |
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ULPD_SAVE(ULPD_STATUS_REQ); |
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ULPD_SAVE(ULPD_DPLL_CTRL); |
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ULPD_SAVE(ULPD_POWER_CTRL); |
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if (cpu_is_omap7xx()) { |
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MPUI7XX_SAVE(MPUI_CTRL); |
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MPUI7XX_SAVE(MPUI_DSP_STATUS); |
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MPUI7XX_SAVE(MPUI_DSP_BOOT_CONFIG); |
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MPUI7XX_SAVE(MPUI_DSP_API_CONFIG); |
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MPUI7XX_SAVE(EMIFF_SDRAM_CONFIG); |
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MPUI7XX_SAVE(EMIFS_CONFIG); |
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} else if (cpu_is_omap15xx()) { |
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MPUI1510_SAVE(MPUI_CTRL); |
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MPUI1510_SAVE(MPUI_DSP_STATUS); |
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MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG); |
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MPUI1510_SAVE(MPUI_DSP_API_CONFIG); |
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MPUI1510_SAVE(EMIFF_SDRAM_CONFIG); |
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MPUI1510_SAVE(EMIFS_CONFIG); |
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} else if (cpu_is_omap16xx()) { |
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MPUI1610_SAVE(MPUI_CTRL); |
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MPUI1610_SAVE(MPUI_DSP_STATUS); |
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MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG); |
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MPUI1610_SAVE(MPUI_DSP_API_CONFIG); |
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MPUI1610_SAVE(EMIFF_SDRAM_CONFIG); |
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MPUI1610_SAVE(EMIFS_CONFIG); |
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} |
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|
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seq_printf(m, |
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"ARM_CKCTL_REG: 0x%-8x \n" |
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"ARM_IDLECT1_REG: 0x%-8x \n" |
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"ARM_IDLECT2_REG: 0x%-8x \n" |
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"ARM_IDLECT3_REG: 0x%-8x \n" |
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"ARM_EWUPCT_REG: 0x%-8x \n" |
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"ARM_RSTCT1_REG: 0x%-8x \n" |
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"ARM_RSTCT2_REG: 0x%-8x \n" |
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"ARM_SYSST_REG: 0x%-8x \n" |
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"ULPD_IT_STATUS_REG: 0x%-4x \n" |
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"ULPD_CLOCK_CTRL_REG: 0x%-4x \n" |
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"ULPD_SOFT_REQ_REG: 0x%-4x \n" |
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"ULPD_DPLL_CTRL_REG: 0x%-4x \n" |
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"ULPD_STATUS_REQ_REG: 0x%-4x \n" |
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"ULPD_POWER_CTRL_REG: 0x%-4x \n", |
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ARM_SHOW(ARM_CKCTL), |
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ARM_SHOW(ARM_IDLECT1), |
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ARM_SHOW(ARM_IDLECT2), |
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ARM_SHOW(ARM_IDLECT3), |
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ARM_SHOW(ARM_EWUPCT), |
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ARM_SHOW(ARM_RSTCT1), |
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ARM_SHOW(ARM_RSTCT2), |
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ARM_SHOW(ARM_SYSST), |
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ULPD_SHOW(ULPD_IT_STATUS), |
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ULPD_SHOW(ULPD_CLOCK_CTRL), |
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ULPD_SHOW(ULPD_SOFT_REQ), |
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ULPD_SHOW(ULPD_DPLL_CTRL), |
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ULPD_SHOW(ULPD_STATUS_REQ), |
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ULPD_SHOW(ULPD_POWER_CTRL)); |
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|
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if (cpu_is_omap7xx()) { |
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seq_printf(m, |
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"MPUI7XX_CTRL_REG 0x%-8x \n" |
|
"MPUI7XX_DSP_STATUS_REG: 0x%-8x \n" |
|
"MPUI7XX_DSP_BOOT_CONFIG_REG: 0x%-8x \n" |
|
"MPUI7XX_DSP_API_CONFIG_REG: 0x%-8x \n" |
|
"MPUI7XX_SDRAM_CONFIG_REG: 0x%-8x \n" |
|
"MPUI7XX_EMIFS_CONFIG_REG: 0x%-8x \n", |
|
MPUI7XX_SHOW(MPUI_CTRL), |
|
MPUI7XX_SHOW(MPUI_DSP_STATUS), |
|
MPUI7XX_SHOW(MPUI_DSP_BOOT_CONFIG), |
|
MPUI7XX_SHOW(MPUI_DSP_API_CONFIG), |
|
MPUI7XX_SHOW(EMIFF_SDRAM_CONFIG), |
|
MPUI7XX_SHOW(EMIFS_CONFIG)); |
|
} else if (cpu_is_omap15xx()) { |
|
seq_printf(m, |
|
"MPUI1510_CTRL_REG 0x%-8x \n" |
|
"MPUI1510_DSP_STATUS_REG: 0x%-8x \n" |
|
"MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n" |
|
"MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n" |
|
"MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n" |
|
"MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n", |
|
MPUI1510_SHOW(MPUI_CTRL), |
|
MPUI1510_SHOW(MPUI_DSP_STATUS), |
|
MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG), |
|
MPUI1510_SHOW(MPUI_DSP_API_CONFIG), |
|
MPUI1510_SHOW(EMIFF_SDRAM_CONFIG), |
|
MPUI1510_SHOW(EMIFS_CONFIG)); |
|
} else if (cpu_is_omap16xx()) { |
|
seq_printf(m, |
|
"MPUI1610_CTRL_REG 0x%-8x \n" |
|
"MPUI1610_DSP_STATUS_REG: 0x%-8x \n" |
|
"MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n" |
|
"MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n" |
|
"MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n" |
|
"MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n", |
|
MPUI1610_SHOW(MPUI_CTRL), |
|
MPUI1610_SHOW(MPUI_DSP_STATUS), |
|
MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG), |
|
MPUI1610_SHOW(MPUI_DSP_API_CONFIG), |
|
MPUI1610_SHOW(EMIFF_SDRAM_CONFIG), |
|
MPUI1610_SHOW(EMIFS_CONFIG)); |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
DEFINE_SHOW_ATTRIBUTE(omap_pm_debug); |
|
|
|
static void omap_pm_init_debugfs(void) |
|
{ |
|
struct dentry *d; |
|
|
|
d = debugfs_create_dir("pm_debug", NULL); |
|
debugfs_create_file("omap_pm", S_IWUSR | S_IRUGO, d, NULL, |
|
&omap_pm_debug_fops); |
|
} |
|
|
|
#endif /* CONFIG_DEBUG_FS */ |
|
|
|
/* |
|
* omap_pm_prepare - Do preliminary suspend work. |
|
* |
|
*/ |
|
static int omap_pm_prepare(void) |
|
{ |
|
/* We cannot sleep in idle until we have resumed */ |
|
cpu_idle_poll_ctrl(true); |
|
return 0; |
|
} |
|
|
|
|
|
/* |
|
* omap_pm_enter - Actually enter a sleep state. |
|
* @state: State we're entering. |
|
* |
|
*/ |
|
|
|
static int omap_pm_enter(suspend_state_t state) |
|
{ |
|
switch (state) |
|
{ |
|
case PM_SUSPEND_MEM: |
|
omap1_pm_suspend(); |
|
break; |
|
default: |
|
return -EINVAL; |
|
} |
|
|
|
return 0; |
|
} |
|
|
|
|
|
/** |
|
* omap_pm_finish - Finish up suspend sequence. |
|
* |
|
* This is called after we wake back up (or if entering the sleep state |
|
* failed). |
|
*/ |
|
|
|
static void omap_pm_finish(void) |
|
{ |
|
cpu_idle_poll_ctrl(false); |
|
} |
|
|
|
|
|
static irqreturn_t omap_wakeup_interrupt(int irq, void *dev) |
|
{ |
|
return IRQ_HANDLED; |
|
} |
|
|
|
|
|
|
|
static const struct platform_suspend_ops omap_pm_ops = { |
|
.prepare = omap_pm_prepare, |
|
.enter = omap_pm_enter, |
|
.finish = omap_pm_finish, |
|
.valid = suspend_valid_only_mem, |
|
}; |
|
|
|
static int __init omap_pm_init(void) |
|
{ |
|
int error = 0; |
|
int irq; |
|
|
|
if (!cpu_class_is_omap1()) |
|
return -ENODEV; |
|
|
|
pr_info("Power Management for TI OMAP.\n"); |
|
|
|
if (!IS_ENABLED(CONFIG_OMAP_32K_TIMER)) |
|
pr_info("OMAP1 PM: sleep states in idle disabled due to no 32KiHz timer\n"); |
|
|
|
if (!IS_ENABLED(CONFIG_OMAP_DM_TIMER)) |
|
pr_info("OMAP1 PM: sleep states in idle disabled due to no DMTIMER support\n"); |
|
|
|
if (IS_ENABLED(CONFIG_OMAP_32K_TIMER) && |
|
IS_ENABLED(CONFIG_OMAP_DM_TIMER)) { |
|
/* OMAP16xx only */ |
|
pr_info("OMAP1 PM: sleep states in idle enabled\n"); |
|
enable_dyn_sleep = 1; |
|
} |
|
|
|
/* |
|
* We copy the assembler sleep/wakeup routines to SRAM. |
|
* These routines need to be in SRAM as that's the only |
|
* memory the MPU can see when it wakes up. |
|
*/ |
|
if (cpu_is_omap7xx()) { |
|
omap_sram_suspend = omap_sram_push(omap7xx_cpu_suspend, |
|
omap7xx_cpu_suspend_sz); |
|
} else if (cpu_is_omap15xx()) { |
|
omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend, |
|
omap1510_cpu_suspend_sz); |
|
} else if (cpu_is_omap16xx()) { |
|
omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend, |
|
omap1610_cpu_suspend_sz); |
|
} |
|
|
|
if (omap_sram_suspend == NULL) { |
|
printk(KERN_ERR "PM not initialized: Missing SRAM support\n"); |
|
return -ENODEV; |
|
} |
|
|
|
arm_pm_idle = omap1_pm_idle; |
|
|
|
if (cpu_is_omap7xx()) |
|
irq = INT_7XX_WAKE_UP_REQ; |
|
else if (cpu_is_omap16xx()) |
|
irq = INT_1610_WAKE_UP_REQ; |
|
else |
|
irq = -1; |
|
|
|
if (irq >= 0) { |
|
if (request_irq(irq, omap_wakeup_interrupt, 0, "peripheral wakeup", NULL)) |
|
pr_err("Failed to request irq %d (peripheral wakeup)\n", irq); |
|
} |
|
|
|
/* Program new power ramp-up time |
|
* (0 for most boards since we don't lower voltage when in deep sleep) |
|
*/ |
|
omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3); |
|
|
|
/* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */ |
|
omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL); |
|
|
|
/* Configure IDLECT3 */ |
|
if (cpu_is_omap7xx()) |
|
omap_writel(OMAP7XX_IDLECT3_VAL, OMAP7XX_IDLECT3); |
|
else if (cpu_is_omap16xx()) |
|
omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3); |
|
|
|
suspend_set_ops(&omap_pm_ops); |
|
|
|
#ifdef CONFIG_DEBUG_FS |
|
omap_pm_init_debugfs(); |
|
#endif |
|
|
|
error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr); |
|
if (error) |
|
printk(KERN_ERR "sysfs_create_file failed: %d\n", error); |
|
|
|
if (cpu_is_omap16xx()) { |
|
/* configure LOW_PWR pin */ |
|
omap_cfg_reg(T20_1610_LOW_PWR); |
|
} |
|
|
|
return error; |
|
} |
|
__initcall(omap_pm_init);
|
|
|