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84 lines
4.0 KiB
84 lines
4.0 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef __ALPHA_MCE_H |
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#define __ALPHA_MCE_H |
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/* |
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* This is the logout header that should be common to all platforms |
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* (assuming they are running OSF/1 PALcode, I guess). |
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*/ |
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struct el_common { |
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unsigned int size; /* size in bytes of logout area */ |
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unsigned int sbz1 : 30; /* should be zero */ |
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unsigned int err2 : 1; /* second error */ |
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unsigned int retry : 1; /* retry flag */ |
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unsigned int proc_offset; /* processor-specific offset */ |
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unsigned int sys_offset; /* system-specific offset */ |
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unsigned int code; /* machine check code */ |
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unsigned int frame_rev; /* frame revision */ |
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}; |
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/* Machine Check Frame for uncorrectable errors (Large format) |
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* --- This is used to log uncorrectable errors such as |
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* double bit ECC errors. |
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* --- These errors are detected by both processor and systems. |
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*/ |
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struct el_common_EV5_uncorrectable_mcheck { |
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unsigned long shadow[8]; /* Shadow reg. 8-14, 25 */ |
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unsigned long paltemp[24]; /* PAL TEMP REGS. */ |
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unsigned long exc_addr; /* Address of excepting instruction*/ |
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unsigned long exc_sum; /* Summary of arithmetic traps. */ |
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unsigned long exc_mask; /* Exception mask (from exc_sum). */ |
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unsigned long pal_base; /* Base address for PALcode. */ |
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unsigned long isr; /* Interrupt Status Reg. */ |
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unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */ |
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unsigned long ic_perr_stat; /* I-CACHE Reg. <11> set Data parity |
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<12> set TAG parity*/ |
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unsigned long dc_perr_stat; /* D-CACHE error Reg. Bits set to 1: |
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<2> Data error in bank 0 |
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<3> Data error in bank 1 |
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<4> Tag error in bank 0 |
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<5> Tag error in bank 1 */ |
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unsigned long va; /* Effective VA of fault or miss. */ |
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unsigned long mm_stat; /* Holds the reason for D-stream |
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fault or D-cache parity errors */ |
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unsigned long sc_addr; /* Address that was being accessed |
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when EV5 detected Secondary cache |
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failure. */ |
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unsigned long sc_stat; /* Helps determine if the error was |
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TAG/Data parity(Secondary Cache)*/ |
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unsigned long bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */ |
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unsigned long ei_addr; /* Physical address of any transfer |
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that is logged in EV5 EI_STAT */ |
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unsigned long fill_syndrome; /* For correcting ECC errors. */ |
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unsigned long ei_stat; /* Helps identify reason of any |
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processor uncorrectable error |
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at its external interface. */ |
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unsigned long ld_lock; /* Contents of EV5 LD_LOCK register*/ |
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}; |
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struct el_common_EV6_mcheck { |
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unsigned int FrameSize; /* Bytes, including this field */ |
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unsigned int FrameFlags; /* <31> = Retry, <30> = Second Error */ |
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unsigned int CpuOffset; /* Offset to CPU-specific info */ |
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unsigned int SystemOffset; /* Offset to system-specific info */ |
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unsigned int MCHK_Code; |
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unsigned int MCHK_Frame_Rev; |
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unsigned long I_STAT; /* EV6 Internal Processor Registers */ |
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unsigned long DC_STAT; /* (See the 21264 Spec) */ |
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unsigned long C_ADDR; |
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unsigned long DC1_SYNDROME; |
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unsigned long DC0_SYNDROME; |
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unsigned long C_STAT; |
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unsigned long C_STS; |
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unsigned long MM_STAT; |
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unsigned long EXC_ADDR; |
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unsigned long IER_CM; |
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unsigned long ISUM; |
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unsigned long RESERVED0; |
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unsigned long PAL_BASE; |
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unsigned long I_CTL; |
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unsigned long PCTX; |
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}; |
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#endif /* __ALPHA_MCE_H */
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