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214 lines
7.8 KiB
214 lines
7.8 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/gpio/nvidia,tegra186-gpio.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: NVIDIA Tegra GPIO Controller (Tegra186 and later) |
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maintainers: |
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- Thierry Reding <[email protected]> |
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- Jon Hunter <[email protected]> |
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description: | |
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Tegra186 contains two GPIO controllers; a main controller and an "AON" |
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controller. This binding document applies to both controllers. The register |
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layouts for the controllers share many similarities, but also some |
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significant differences. Hence, this document describes closely related but |
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different bindings and compatible values. |
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The Tegra186 GPIO controller allows software to set the IO direction of, |
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and read/write the value of, numerous GPIO signals. Routing of GPIO signals |
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to package balls is under the control of a separate pin controller hardware |
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block. Two major sets of registers exist: |
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a) Security registers, which allow configuration of allowed access to the |
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GPIO register set. These registers exist in a single contiguous block |
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of physical address space. The size of this block, and the security |
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features available, varies between the different GPIO controllers. |
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Access to this set of registers is not necessary in all circumstances. |
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Code that wishes to configure access to the GPIO registers needs access |
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to these registers to do so. Code which simply wishes to read or write |
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GPIO data does not need access to these registers. |
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b) GPIO registers, which allow manipulation of the GPIO signals. In some |
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GPIO controllers, these registers are exposed via multiple "physical |
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aliases" in address space, each of which access the same underlying |
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state. See the hardware documentation for rationale. Any particular |
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GPIO client is expected to access just one of these physical aliases. |
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Tegra HW documentation describes a unified naming convention for all GPIOs |
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implemented by the SoC. Each GPIO is assigned to a port, and a port may |
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control a number of GPIOs. Thus, each GPIO is named according to an |
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alphabetical port name and an integer GPIO name within the port. For |
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example, GPIO_PA0, GPIO_PN6, or GPIO_PCC3. |
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The number of ports implemented by each GPIO controller varies. The number |
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of implemented GPIOs within each port varies. GPIO registers within a |
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controller are grouped and laid out according to the port they affect. |
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The mapping from port name to the GPIO controller that implements that |
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port, and the mapping from port name to register offset within a |
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controller, are both extremely non-linear. The header file |
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<dt-bindings/gpio/tegra186-gpio.h> describes the port-level mapping. In |
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that file, the naming convention for ports matches the HW documentation. |
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The values chosen for the names are alphabetically sorted within a |
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particular controller. Drivers need to map between the DT GPIO IDs and HW |
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register offsets using a lookup table. |
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Each GPIO controller can generate a number of interrupt signals. Each |
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signal represents the aggregate status for all GPIOs within a set of |
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ports. Thus, the number of interrupt signals generated by a controller |
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varies as a rough function of the number of ports it implements. Note |
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that the HW documentation refers to both the overall controller HW |
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module and the sets-of-ports as "controllers". |
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Each GPIO controller in fact generates multiple interrupts signals for |
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each set of ports. Each GPIO may be configured to feed into a specific |
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one of the interrupt signals generated by a set-of-ports. The intent is |
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for each generated signal to be routed to a different CPU, thus allowing |
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different CPUs to each handle subsets of the interrupts within a port. |
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The status of each of these per-port-set signals is reported via a |
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separate register. Thus, a driver needs to know which status register to |
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observe. This binding currently defines no configuration mechanism for |
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this. By default, drivers should use register |
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GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could |
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define a property to configure this. |
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properties: |
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compatible: |
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enum: |
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- nvidia,tegra186-gpio |
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- nvidia,tegra186-gpio-aon |
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- nvidia,tegra194-gpio |
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- nvidia,tegra194-gpio-aon |
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- nvidia,tegra234-gpio |
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- nvidia,tegra234-gpio-aon |
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reg-names: |
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items: |
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- const: security |
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- const: gpio |
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minItems: 1 |
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reg: |
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items: |
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- description: Security configuration registers. |
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- description: | |
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GPIO control registers. This may cover either: |
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a) The single physical alias that this OS should use. |
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b) All physical aliases that exist in the controller. This is |
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appropriate when the OS is responsible for managing assignment |
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of the physical aliases. |
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minItems: 1 |
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interrupts: |
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description: The interrupt outputs from the HW block, one per set of |
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ports, in the order the HW manual describes them. The number of entries |
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required varies depending on compatible value. |
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gpio-controller: true |
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"#gpio-cells": |
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description: | |
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Indicates how many cells are used in a consumer's GPIO specifier. In the |
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specifier: |
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- The first cell is the pin number. |
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See <dt-bindings/gpio/tegra186-gpio.h>. |
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- The second cell contains flags: |
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- Bit 0 specifies polarity |
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- 0: Active-high (normal). |
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- 1: Active-low (inverted). |
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const: 2 |
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interrupt-controller: true |
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"#interrupt-cells": |
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description: | |
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Indicates how many cells are used in a consumer's interrupt specifier. |
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In the specifier: |
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- The first cell is the GPIO number. |
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See <dt-bindings/gpio/tegra186-gpio.h>. |
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- The second cell is contains flags: |
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- Bits [3:0] indicate trigger type and level: |
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- 1: Low-to-high edge triggered. |
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- 2: High-to-low edge triggered. |
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- 4: Active high level-sensitive. |
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- 8: Active low level-sensitive. |
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Valid combinations are 1, 2, 3, 4, 8. |
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const: 2 |
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allOf: |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- nvidia,tegra186-gpio |
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- nvidia,tegra194-gpio |
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- nvidia,tegra234-gpio |
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then: |
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properties: |
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interrupts: |
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minItems: 6 |
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maxItems: 48 |
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- if: |
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properties: |
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compatible: |
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contains: |
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enum: |
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- nvidia,tegra186-gpio-aon |
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- nvidia,tegra194-gpio-aon |
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- nvidia,tegra234-gpio-aon |
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then: |
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properties: |
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interrupts: |
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minItems: 1 |
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maxItems: 4 |
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required: |
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- compatible |
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- reg |
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- reg-names |
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- interrupts |
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additionalProperties: false |
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examples: |
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- | |
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#include <dt-bindings/interrupt-controller/irq.h> |
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gpio@2200000 { |
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compatible = "nvidia,tegra186-gpio"; |
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reg-names = "security", "gpio"; |
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reg = <0x2200000 0x10000>, |
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<0x2210000 0x10000>; |
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interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>, |
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<0 50 IRQ_TYPE_LEVEL_HIGH>, |
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<0 53 IRQ_TYPE_LEVEL_HIGH>, |
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<0 56 IRQ_TYPE_LEVEL_HIGH>, |
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<0 59 IRQ_TYPE_LEVEL_HIGH>, |
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<0 180 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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}; |
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gpio@c2f0000 { |
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compatible = "nvidia,tegra186-gpio-aon"; |
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reg-names = "security", "gpio"; |
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reg = <0xc2f0000 0x1000>, |
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<0xc2f1000 0x1000>; |
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interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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};
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