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172 lines
3.9 KiB
172 lines
3.9 KiB
Qualcomm Technologies, Inc. CPUFREQ Bindings |
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CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI) |
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SoCs to manage frequency in hardware. It is capable of controlling frequency |
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for multiple clusters. |
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Properties: |
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- compatible |
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Usage: required |
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Value type: <string> |
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Definition: must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss". |
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- clocks |
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Usage: required |
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Value type: <phandle> From common clock binding. |
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Definition: clock handle for XO clock and GPLL0 clock. |
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- clock-names |
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Usage: required |
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Value type: <string> From common clock binding. |
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Definition: must be "xo", "alternate". |
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- reg |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: Addresses and sizes for the memory of the HW bases in |
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each frequency domain. |
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- reg-names |
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Usage: Optional |
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Value type: <string> |
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Definition: Frequency domain name i.e. |
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"freq-domain0", "freq-domain1". |
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- #freq-domain-cells: |
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Usage: required. |
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Definition: Number of cells in a freqency domain specifier. |
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* Property qcom,freq-domain |
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Devices supporting freq-domain must set their "qcom,freq-domain" property with |
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phandle to a cpufreq_hw followed by the Domain ID(0/1) in the CPU DT node. |
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Example: |
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Example 1: Dual-cluster, Quad-core per cluster. CPUs within a cluster switch |
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DCVS state together. |
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/ { |
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cpus { |
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#address-cells = <2>; |
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#size-cells = <0>; |
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CPU0: cpu@0 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x0>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_0>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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L2_0: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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L3_0: l3-cache { |
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compatible = "cache"; |
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}; |
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}; |
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}; |
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CPU1: cpu@100 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x100>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_100>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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L2_100: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU2: cpu@200 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x200>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_200>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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L2_200: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU3: cpu@300 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x300>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_300>; |
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qcom,freq-domain = <&cpufreq_hw 0>; |
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L2_300: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU4: cpu@400 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x400>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_400>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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L2_400: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU5: cpu@500 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x500>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_500>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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L2_500: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU6: cpu@600 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x600>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_600>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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L2_600: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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CPU7: cpu@700 { |
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device_type = "cpu"; |
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compatible = "qcom,kryo385"; |
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reg = <0x0 0x700>; |
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enable-method = "psci"; |
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next-level-cache = <&L2_700>; |
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qcom,freq-domain = <&cpufreq_hw 1>; |
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L2_700: l2-cache { |
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compatible = "cache"; |
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next-level-cache = <&L3_0>; |
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}; |
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}; |
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}; |
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soc { |
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cpufreq_hw: cpufreq@17d43000 { |
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compatible = "qcom,cpufreq-hw"; |
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reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>; |
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reg-names = "freq-domain0", "freq-domain1"; |
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; |
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clock-names = "xo", "alternate"; |
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#freq-domain-cells = <1>; |
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}; |
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}
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