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103 lines
3.2 KiB
103 lines
3.2 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Cannonlake SST DSP Support |
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* |
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* Copyright (C) 2016-17, Intel Corporation. |
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*/ |
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#ifndef __CNL_SST_DSP_H__ |
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#define __CNL_SST_DSP_H__ |
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struct sst_dsp; |
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struct sst_dsp_device; |
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struct sst_generic_ipc; |
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/* Intel HD Audio General DSP Registers */ |
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#define CNL_ADSP_GEN_BASE 0x0 |
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#define CNL_ADSP_REG_ADSPCS (CNL_ADSP_GEN_BASE + 0x04) |
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#define CNL_ADSP_REG_ADSPIC (CNL_ADSP_GEN_BASE + 0x08) |
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#define CNL_ADSP_REG_ADSPIS (CNL_ADSP_GEN_BASE + 0x0c) |
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/* Intel HD Audio Inter-Processor Communication Registers */ |
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#define CNL_ADSP_IPC_BASE 0xc0 |
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#define CNL_ADSP_REG_HIPCTDR (CNL_ADSP_IPC_BASE + 0x00) |
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#define CNL_ADSP_REG_HIPCTDA (CNL_ADSP_IPC_BASE + 0x04) |
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#define CNL_ADSP_REG_HIPCTDD (CNL_ADSP_IPC_BASE + 0x08) |
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#define CNL_ADSP_REG_HIPCIDR (CNL_ADSP_IPC_BASE + 0x10) |
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#define CNL_ADSP_REG_HIPCIDA (CNL_ADSP_IPC_BASE + 0x14) |
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#define CNL_ADSP_REG_HIPCIDD (CNL_ADSP_IPC_BASE + 0x18) |
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#define CNL_ADSP_REG_HIPCCTL (CNL_ADSP_IPC_BASE + 0x28) |
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/* HIPCTDR */ |
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#define CNL_ADSP_REG_HIPCTDR_BUSY BIT(31) |
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/* HIPCTDA */ |
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#define CNL_ADSP_REG_HIPCTDA_DONE BIT(31) |
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/* HIPCIDR */ |
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#define CNL_ADSP_REG_HIPCIDR_BUSY BIT(31) |
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/* HIPCIDA */ |
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#define CNL_ADSP_REG_HIPCIDA_DONE BIT(31) |
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/* CNL HIPCCTL */ |
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#define CNL_ADSP_REG_HIPCCTL_DONE BIT(1) |
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#define CNL_ADSP_REG_HIPCCTL_BUSY BIT(0) |
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/* CNL HIPCT */ |
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#define CNL_ADSP_REG_HIPCT_BUSY BIT(31) |
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/* Intel HD Audio SRAM Window 1 */ |
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#define CNL_ADSP_SRAM1_BASE 0xa0000 |
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#define CNL_ADSP_MMIO_LEN 0x10000 |
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#define CNL_ADSP_W0_STAT_SZ 0x1000 |
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#define CNL_ADSP_W0_UP_SZ 0x1000 |
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#define CNL_ADSP_W1_SZ 0x1000 |
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#define CNL_FW_STS_MASK 0xf |
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#define CNL_ADSPIC_IPC 0x1 |
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#define CNL_ADSPIS_IPC 0x1 |
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#define CNL_DSP_CORES 4 |
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#define CNL_DSP_CORES_MASK ((1 << CNL_DSP_CORES) - 1) |
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/* core reset - asserted high */ |
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#define CNL_ADSPCS_CRST_SHIFT 0 |
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#define CNL_ADSPCS_CRST(x) (x << CNL_ADSPCS_CRST_SHIFT) |
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/* core run/stall - when set to 1 core is stalled */ |
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#define CNL_ADSPCS_CSTALL_SHIFT 8 |
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#define CNL_ADSPCS_CSTALL(x) (x << CNL_ADSPCS_CSTALL_SHIFT) |
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/* set power active - when set to 1 turn core on */ |
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#define CNL_ADSPCS_SPA_SHIFT 16 |
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#define CNL_ADSPCS_SPA(x) (x << CNL_ADSPCS_SPA_SHIFT) |
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/* current power active - power status of cores, set by hardware */ |
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#define CNL_ADSPCS_CPA_SHIFT 24 |
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#define CNL_ADSPCS_CPA(x) (x << CNL_ADSPCS_CPA_SHIFT) |
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int cnl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask); |
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int cnl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask); |
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irqreturn_t cnl_dsp_sst_interrupt(int irq, void *dev_id); |
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void cnl_dsp_free(struct sst_dsp *dsp); |
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void cnl_ipc_int_enable(struct sst_dsp *ctx); |
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void cnl_ipc_int_disable(struct sst_dsp *ctx); |
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void cnl_ipc_op_int_enable(struct sst_dsp *ctx); |
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void cnl_ipc_op_int_disable(struct sst_dsp *ctx); |
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bool cnl_ipc_int_status(struct sst_dsp *ctx); |
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void cnl_ipc_free(struct sst_generic_ipc *ipc); |
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int cnl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq, |
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const char *fw_name, struct skl_dsp_loader_ops dsp_ops, |
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struct skl_dev **dsp); |
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int cnl_sst_init_fw(struct device *dev, struct skl_dev *skl); |
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void cnl_sst_dsp_cleanup(struct device *dev, struct skl_dev *skl); |
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#endif /*__CNL_SST_DSP_H__*/
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