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178 lines
5.7 KiB
178 lines
5.7 KiB
/* SPDX-License-Identifier: GPL-2.0-only */ |
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/* |
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* Copyright(c) 2020 Intel Corporation. All rights reserved. |
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* |
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* Author: Cezary Rojewski <[email protected]> |
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*/ |
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#ifndef __SND_SOC_INTEL_CATPT_REGS_H |
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#define __SND_SOC_INTEL_CATPT_REGS_H |
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#include <linux/bitops.h> |
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#include <linux/iopoll.h> |
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#include <uapi/linux/pci_regs.h> |
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#define CATPT_SHIM_REGS_SIZE 4096 |
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#define CATPT_DMA_REGS_SIZE 1024 |
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#define CATPT_DMA_COUNT 2 |
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#define CATPT_SSP_REGS_SIZE 512 |
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/* DSP Shim registers */ |
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#define CATPT_SHIM_CS1 0x00 |
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#define CATPT_SHIM_ISC 0x18 |
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#define CATPT_SHIM_ISD 0x20 |
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#define CATPT_SHIM_IMC 0x28 |
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#define CATPT_SHIM_IMD 0x30 |
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#define CATPT_SHIM_IPCC 0x38 |
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#define CATPT_SHIM_IPCD 0x40 |
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#define CATPT_SHIM_CLKCTL 0x78 |
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#define CATPT_SHIM_CS2 0x80 |
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#define CATPT_SHIM_LTRC 0xE0 |
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#define CATPT_SHIM_HMDC 0xE8 |
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#define CATPT_CS_LPCS BIT(31) |
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#define CATPT_CS_SFCR(ssp) BIT(27 + (ssp)) |
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#define CATPT_CS_S1IOCS BIT(23) |
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#define CATPT_CS_S0IOCS BIT(21) |
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#define CATPT_CS_PCE BIT(15) |
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#define CATPT_CS_SDPM(ssp) BIT(11 + (ssp)) |
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#define CATPT_CS_STALL BIT(10) |
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#define CATPT_CS_DCS GENMASK(6, 4) |
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/* b100 DSP core & audio fabric high clock */ |
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#define CATPT_CS_DCS_HIGH (0x4 << 4) |
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#define CATPT_CS_SBCS(ssp) BIT(2 + (ssp)) |
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#define CATPT_CS_RST BIT(1) |
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#define CATPT_ISC_IPCDB BIT(1) |
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#define CATPT_ISC_IPCCD BIT(0) |
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#define CATPT_ISD_DCPWM BIT(31) |
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#define CATPT_ISD_IPCCB BIT(1) |
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#define CATPT_ISD_IPCDD BIT(0) |
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#define CATPT_IMC_IPCDB BIT(1) |
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#define CATPT_IMC_IPCCD BIT(0) |
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#define CATPT_IMD_IPCCB BIT(1) |
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#define CATPT_IMD_IPCDD BIT(0) |
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#define CATPT_IPCC_BUSY BIT(31) |
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#define CATPT_IPCC_DONE BIT(30) |
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#define CATPT_IPCD_BUSY BIT(31) |
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#define CATPT_IPCD_DONE BIT(30) |
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#define CATPT_CLKCTL_CFCIP BIT(31) |
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#define CATPT_CLKCTL_SMOS GENMASK(25, 24) |
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#define CATPT_HMDC_HDDA(e, ch) BIT(8 * (e) + (ch)) |
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/* defaults to reset SHIM registers to after each power cycle */ |
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#define CATPT_CS_DEFAULT 0x8480040E |
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#define CATPT_ISC_DEFAULT 0x0 |
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#define CATPT_ISD_DEFAULT 0x0 |
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#define CATPT_IMC_DEFAULT 0x7FFF0003 |
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#define CATPT_IMD_DEFAULT 0x7FFF0003 |
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#define CATPT_IPCC_DEFAULT 0x0 |
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#define CATPT_IPCD_DEFAULT 0x0 |
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#define CATPT_CLKCTL_DEFAULT 0x7FF |
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#define CATPT_CS2_DEFAULT 0x0 |
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#define CATPT_LTRC_DEFAULT 0x0 |
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#define CATPT_HMDC_DEFAULT 0x0 |
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/* PCI Configuration registers */ |
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#define CATPT_PCI_PMCAPID 0x80 |
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#define CATPT_PCI_PMCS (CATPT_PCI_PMCAPID + PCI_PM_CTRL) |
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#define CATPT_PCI_VDRTCTL0 0xA0 |
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#define CATPT_PCI_VDRTCTL2 0xA8 |
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#define CATPT_VDRTCTL2_DTCGE BIT(10) |
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#define CATPT_VDRTCTL2_DCLCGE BIT(1) |
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#define CATPT_VDRTCTL2_CGEALL 0xF7F |
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/* LPT PCI Configuration bits */ |
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#define LPT_VDRTCTL0_DSRAMPGE(b) BIT(16 + (b)) |
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#define LPT_VDRTCTL0_DSRAMPGE_MASK GENMASK(31, 16) |
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#define LPT_VDRTCTL0_ISRAMPGE(b) BIT(6 + (b)) |
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#define LPT_VDRTCTL0_ISRAMPGE_MASK GENMASK(15, 6) |
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#define LPT_VDRTCTL0_D3SRAMPGD BIT(2) |
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#define LPT_VDRTCTL0_D3PGD BIT(1) |
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#define LPT_VDRTCTL0_APLLSE BIT(0) |
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/* WPT PCI Configuration bits */ |
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#define WPT_VDRTCTL0_DSRAMPGE(b) BIT(12 + (b)) |
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#define WPT_VDRTCTL0_DSRAMPGE_MASK GENMASK(31, 12) |
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#define WPT_VDRTCTL0_ISRAMPGE(b) BIT(2 + (b)) |
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#define WPT_VDRTCTL0_ISRAMPGE_MASK GENMASK(11, 2) |
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#define WPT_VDRTCTL0_D3SRAMPGD BIT(1) |
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#define WPT_VDRTCTL0_D3PGD BIT(0) |
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#define WPT_VDRTCTL2_APLLSE BIT(31) |
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/* defaults to reset SSP registers to after each power cycle */ |
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#define CATPT_SSC0_DEFAULT 0x0 |
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#define CATPT_SSC1_DEFAULT 0x0 |
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#define CATPT_SSS_DEFAULT 0xF004 |
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#define CATPT_SSIT_DEFAULT 0x0 |
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#define CATPT_SSD_DEFAULT 0xC43893A3 |
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#define CATPT_SSTO_DEFAULT 0x0 |
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#define CATPT_SSPSP_DEFAULT 0x0 |
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#define CATPT_SSTSA_DEFAULT 0x0 |
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#define CATPT_SSRSA_DEFAULT 0x0 |
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#define CATPT_SSTSS_DEFAULT 0x0 |
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#define CATPT_SSCR2_DEFAULT 0x0 |
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#define CATPT_SSPSP2_DEFAULT 0x0 |
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/* Physically the same block, access address differs between host and dsp */ |
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#define CATPT_DSP_DRAM_OFFSET 0x400000 |
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#define catpt_to_host_offset(offset) ((offset) & ~(CATPT_DSP_DRAM_OFFSET)) |
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#define catpt_to_dsp_offset(offset) ((offset) | CATPT_DSP_DRAM_OFFSET) |
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#define CATPT_MEMBLOCK_SIZE 0x8000 |
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#define catpt_num_dram(cdev) (hweight_long((cdev)->spec->dram_mask)) |
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#define catpt_num_iram(cdev) (hweight_long((cdev)->spec->iram_mask)) |
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#define catpt_dram_size(cdev) (catpt_num_dram(cdev) * CATPT_MEMBLOCK_SIZE) |
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#define catpt_iram_size(cdev) (catpt_num_iram(cdev) * CATPT_MEMBLOCK_SIZE) |
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/* registry I/O helpers */ |
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#define catpt_shim_addr(cdev) \ |
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((cdev)->lpe_ba + (cdev)->spec->host_shim_offset) |
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#define catpt_dma_addr(cdev, dma) \ |
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((cdev)->lpe_ba + (cdev)->spec->host_dma_offset[dma]) |
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#define catpt_ssp_addr(cdev, ssp) \ |
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((cdev)->lpe_ba + (cdev)->spec->host_ssp_offset[ssp]) |
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#define catpt_inbox_addr(cdev) \ |
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((cdev)->lpe_ba + (cdev)->ipc.config.inbox_offset) |
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#define catpt_outbox_addr(cdev) \ |
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((cdev)->lpe_ba + (cdev)->ipc.config.outbox_offset) |
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#define catpt_writel_ssp(cdev, ssp, reg, val) \ |
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writel(val, catpt_ssp_addr(cdev, ssp) + (reg)) |
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#define catpt_readl_shim(cdev, reg) \ |
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readl(catpt_shim_addr(cdev) + CATPT_SHIM_##reg) |
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#define catpt_writel_shim(cdev, reg, val) \ |
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writel(val, catpt_shim_addr(cdev) + CATPT_SHIM_##reg) |
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#define catpt_updatel_shim(cdev, reg, mask, val) \ |
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catpt_writel_shim(cdev, reg, \ |
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(catpt_readl_shim(cdev, reg) & ~(mask)) | (val)) |
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#define catpt_readl_poll_shim(cdev, reg, val, cond, delay_us, timeout_us) \ |
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readl_poll_timeout(catpt_shim_addr(cdev) + CATPT_SHIM_##reg, \ |
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val, cond, delay_us, timeout_us) |
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#define catpt_readl_pci(cdev, reg) \ |
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readl(cdev->pci_ba + CATPT_PCI_##reg) |
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#define catpt_writel_pci(cdev, reg, val) \ |
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writel(val, cdev->pci_ba + CATPT_PCI_##reg) |
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#define catpt_updatel_pci(cdev, reg, mask, val) \ |
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catpt_writel_pci(cdev, reg, \ |
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(catpt_readl_pci(cdev, reg) & ~(mask)) | (val)) |
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#define catpt_readl_poll_pci(cdev, reg, val, cond, delay_us, timeout_us) \ |
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readl_poll_timeout((cdev)->pci_ba + CATPT_PCI_##reg, \ |
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val, cond, delay_us, timeout_us) |
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#endif
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