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649 lines
16 KiB
649 lines
16 KiB
// SPDX-License-Identifier: GPL-2.0 |
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/* |
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* Library implementing the most common irq chip callback functions |
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* |
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* Copyright (C) 2011, Thomas Gleixner |
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*/ |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/slab.h> |
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#include <linux/export.h> |
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#include <linux/irqdomain.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel_stat.h> |
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#include <linux/syscore_ops.h> |
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#include "internals.h" |
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static LIST_HEAD(gc_list); |
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static DEFINE_RAW_SPINLOCK(gc_lock); |
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/** |
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* irq_gc_noop - NOOP function |
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* @d: irq_data |
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*/ |
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void irq_gc_noop(struct irq_data *d) |
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{ |
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} |
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/** |
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* irq_gc_mask_disable_reg - Mask chip via disable register |
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* @d: irq_data |
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* |
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* Chip has separate enable/disable registers instead of a single mask |
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* register. |
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*/ |
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void irq_gc_mask_disable_reg(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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u32 mask = d->mask; |
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irq_gc_lock(gc); |
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irq_reg_writel(gc, mask, ct->regs.disable); |
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*ct->mask_cache &= ~mask; |
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irq_gc_unlock(gc); |
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} |
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/** |
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* irq_gc_mask_set_bit - Mask chip via setting bit in mask register |
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* @d: irq_data |
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* |
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* Chip has a single mask register. Values of this register are cached |
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* and protected by gc->lock |
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*/ |
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void irq_gc_mask_set_bit(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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u32 mask = d->mask; |
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irq_gc_lock(gc); |
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*ct->mask_cache |= mask; |
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irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); |
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irq_gc_unlock(gc); |
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} |
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EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit); |
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/** |
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* irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register |
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* @d: irq_data |
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* |
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* Chip has a single mask register. Values of this register are cached |
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* and protected by gc->lock |
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*/ |
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void irq_gc_mask_clr_bit(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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u32 mask = d->mask; |
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irq_gc_lock(gc); |
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*ct->mask_cache &= ~mask; |
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irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask); |
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irq_gc_unlock(gc); |
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} |
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EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit); |
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/** |
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* irq_gc_unmask_enable_reg - Unmask chip via enable register |
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* @d: irq_data |
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* |
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* Chip has separate enable/disable registers instead of a single mask |
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* register. |
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*/ |
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void irq_gc_unmask_enable_reg(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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u32 mask = d->mask; |
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irq_gc_lock(gc); |
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irq_reg_writel(gc, mask, ct->regs.enable); |
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*ct->mask_cache |= mask; |
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irq_gc_unlock(gc); |
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} |
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/** |
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* irq_gc_ack_set_bit - Ack pending interrupt via setting bit |
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* @d: irq_data |
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*/ |
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void irq_gc_ack_set_bit(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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u32 mask = d->mask; |
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irq_gc_lock(gc); |
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irq_reg_writel(gc, mask, ct->regs.ack); |
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irq_gc_unlock(gc); |
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} |
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EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit); |
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/** |
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* irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit |
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* @d: irq_data |
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*/ |
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void irq_gc_ack_clr_bit(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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u32 mask = ~d->mask; |
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irq_gc_lock(gc); |
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irq_reg_writel(gc, mask, ct->regs.ack); |
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irq_gc_unlock(gc); |
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} |
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/** |
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* irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt |
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* @d: irq_data |
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* |
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* This generic implementation of the irq_mask_ack method is for chips |
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* with separate enable/disable registers instead of a single mask |
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* register and where a pending interrupt is acknowledged by setting a |
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* bit. |
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* |
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* Note: This is the only permutation currently used. Similar generic |
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* functions should be added here if other permutations are required. |
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*/ |
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void irq_gc_mask_disable_and_ack_set(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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u32 mask = d->mask; |
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irq_gc_lock(gc); |
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irq_reg_writel(gc, mask, ct->regs.disable); |
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*ct->mask_cache &= ~mask; |
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irq_reg_writel(gc, mask, ct->regs.ack); |
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irq_gc_unlock(gc); |
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} |
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/** |
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* irq_gc_eoi - EOI interrupt |
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* @d: irq_data |
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*/ |
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void irq_gc_eoi(struct irq_data *d) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = irq_data_get_chip_type(d); |
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u32 mask = d->mask; |
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irq_gc_lock(gc); |
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irq_reg_writel(gc, mask, ct->regs.eoi); |
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irq_gc_unlock(gc); |
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} |
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/** |
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* irq_gc_set_wake - Set/clr wake bit for an interrupt |
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* @d: irq_data |
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* @on: Indicates whether the wake bit should be set or cleared |
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* |
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* For chips where the wake from suspend functionality is not |
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* configured in a separate register and the wakeup active state is |
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* just stored in a bitmask. |
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*/ |
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int irq_gc_set_wake(struct irq_data *d, unsigned int on) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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u32 mask = d->mask; |
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if (!(mask & gc->wake_enabled)) |
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return -EINVAL; |
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irq_gc_lock(gc); |
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if (on) |
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gc->wake_active |= mask; |
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else |
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gc->wake_active &= ~mask; |
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irq_gc_unlock(gc); |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(irq_gc_set_wake); |
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static u32 irq_readl_be(void __iomem *addr) |
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{ |
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return ioread32be(addr); |
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} |
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static void irq_writel_be(u32 val, void __iomem *addr) |
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{ |
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iowrite32be(val, addr); |
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} |
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void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name, |
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int num_ct, unsigned int irq_base, |
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void __iomem *reg_base, irq_flow_handler_t handler) |
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{ |
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raw_spin_lock_init(&gc->lock); |
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gc->num_ct = num_ct; |
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gc->irq_base = irq_base; |
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gc->reg_base = reg_base; |
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gc->chip_types->chip.name = name; |
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gc->chip_types->handler = handler; |
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} |
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/** |
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* irq_alloc_generic_chip - Allocate a generic chip and initialize it |
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* @name: Name of the irq chip |
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* @num_ct: Number of irq_chip_type instances associated with this |
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* @irq_base: Interrupt base nr for this chip |
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* @reg_base: Register base address (virtual) |
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* @handler: Default flow handler associated with this chip |
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* |
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* Returns an initialized irq_chip_generic structure. The chip defaults |
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* to the primary (index 0) irq_chip_type and @handler |
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*/ |
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struct irq_chip_generic * |
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irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base, |
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void __iomem *reg_base, irq_flow_handler_t handler) |
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{ |
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struct irq_chip_generic *gc; |
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unsigned long sz = sizeof(*gc) + num_ct * sizeof(struct irq_chip_type); |
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gc = kzalloc(sz, GFP_KERNEL); |
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if (gc) { |
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irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base, |
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handler); |
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} |
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return gc; |
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} |
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EXPORT_SYMBOL_GPL(irq_alloc_generic_chip); |
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static void |
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irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags) |
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{ |
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struct irq_chip_type *ct = gc->chip_types; |
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u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask; |
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int i; |
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for (i = 0; i < gc->num_ct; i++) { |
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if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) { |
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mskptr = &ct[i].mask_cache_priv; |
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mskreg = ct[i].regs.mask; |
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} |
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ct[i].mask_cache = mskptr; |
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if (flags & IRQ_GC_INIT_MASK_CACHE) |
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*mskptr = irq_reg_readl(gc, mskreg); |
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} |
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} |
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/** |
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* __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain |
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* @d: irq domain for which to allocate chips |
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* @irqs_per_chip: Number of interrupts each chip handles (max 32) |
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* @num_ct: Number of irq_chip_type instances associated with this |
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* @name: Name of the irq chip |
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* @handler: Default flow handler associated with these chips |
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* @clr: IRQ_* bits to clear in the mapping function |
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* @set: IRQ_* bits to set in the mapping function |
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* @gcflags: Generic chip specific setup flags |
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*/ |
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int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip, |
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int num_ct, const char *name, |
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irq_flow_handler_t handler, |
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unsigned int clr, unsigned int set, |
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enum irq_gc_flags gcflags) |
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{ |
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struct irq_domain_chip_generic *dgc; |
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struct irq_chip_generic *gc; |
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int numchips, sz, i; |
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unsigned long flags; |
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void *tmp; |
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if (d->gc) |
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return -EBUSY; |
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numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip); |
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if (!numchips) |
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return -EINVAL; |
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/* Allocate a pointer, generic chip and chiptypes for each chip */ |
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sz = sizeof(*dgc) + numchips * sizeof(gc); |
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sz += numchips * (sizeof(*gc) + num_ct * sizeof(struct irq_chip_type)); |
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tmp = dgc = kzalloc(sz, GFP_KERNEL); |
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if (!dgc) |
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return -ENOMEM; |
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dgc->irqs_per_chip = irqs_per_chip; |
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dgc->num_chips = numchips; |
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dgc->irq_flags_to_set = set; |
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dgc->irq_flags_to_clear = clr; |
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dgc->gc_flags = gcflags; |
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d->gc = dgc; |
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/* Calc pointer to the first generic chip */ |
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tmp += sizeof(*dgc) + numchips * sizeof(gc); |
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for (i = 0; i < numchips; i++) { |
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/* Store the pointer to the generic chip */ |
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dgc->gc[i] = gc = tmp; |
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irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip, |
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NULL, handler); |
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gc->domain = d; |
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if (gcflags & IRQ_GC_BE_IO) { |
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gc->reg_readl = &irq_readl_be; |
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gc->reg_writel = &irq_writel_be; |
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} |
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raw_spin_lock_irqsave(&gc_lock, flags); |
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list_add_tail(&gc->list, &gc_list); |
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raw_spin_unlock_irqrestore(&gc_lock, flags); |
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/* Calc pointer to the next generic chip */ |
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tmp += sizeof(*gc) + num_ct * sizeof(struct irq_chip_type); |
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} |
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return 0; |
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} |
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EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips); |
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static struct irq_chip_generic * |
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__irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq) |
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{ |
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struct irq_domain_chip_generic *dgc = d->gc; |
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int idx; |
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if (!dgc) |
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return ERR_PTR(-ENODEV); |
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idx = hw_irq / dgc->irqs_per_chip; |
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if (idx >= dgc->num_chips) |
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return ERR_PTR(-EINVAL); |
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return dgc->gc[idx]; |
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} |
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/** |
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* irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq |
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* @d: irq domain pointer |
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* @hw_irq: Hardware interrupt number |
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*/ |
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struct irq_chip_generic * |
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irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq) |
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{ |
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struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq); |
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return !IS_ERR(gc) ? gc : NULL; |
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} |
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EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip); |
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/* |
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* Separate lockdep classes for interrupt chip which can nest irq_desc |
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* lock and request mutex. |
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*/ |
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static struct lock_class_key irq_nested_lock_class; |
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static struct lock_class_key irq_nested_request_class; |
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/* |
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* irq_map_generic_chip - Map a generic chip for an irq domain |
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*/ |
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int irq_map_generic_chip(struct irq_domain *d, unsigned int virq, |
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irq_hw_number_t hw_irq) |
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{ |
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struct irq_data *data = irq_domain_get_irq_data(d, virq); |
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struct irq_domain_chip_generic *dgc = d->gc; |
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struct irq_chip_generic *gc; |
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struct irq_chip_type *ct; |
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struct irq_chip *chip; |
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unsigned long flags; |
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int idx; |
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gc = __irq_get_domain_generic_chip(d, hw_irq); |
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if (IS_ERR(gc)) |
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return PTR_ERR(gc); |
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idx = hw_irq % dgc->irqs_per_chip; |
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if (test_bit(idx, &gc->unused)) |
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return -ENOTSUPP; |
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if (test_bit(idx, &gc->installed)) |
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return -EBUSY; |
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ct = gc->chip_types; |
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chip = &ct->chip; |
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/* We only init the cache for the first mapping of a generic chip */ |
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if (!gc->installed) { |
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raw_spin_lock_irqsave(&gc->lock, flags); |
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irq_gc_init_mask_cache(gc, dgc->gc_flags); |
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raw_spin_unlock_irqrestore(&gc->lock, flags); |
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} |
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/* Mark the interrupt as installed */ |
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set_bit(idx, &gc->installed); |
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if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK) |
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irq_set_lockdep_class(virq, &irq_nested_lock_class, |
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&irq_nested_request_class); |
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if (chip->irq_calc_mask) |
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chip->irq_calc_mask(data); |
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else |
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data->mask = 1 << idx; |
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irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL); |
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irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set); |
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return 0; |
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} |
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static void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq) |
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{ |
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struct irq_data *data = irq_domain_get_irq_data(d, virq); |
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struct irq_domain_chip_generic *dgc = d->gc; |
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unsigned int hw_irq = data->hwirq; |
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struct irq_chip_generic *gc; |
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int irq_idx; |
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gc = irq_get_domain_generic_chip(d, hw_irq); |
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if (!gc) |
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return; |
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irq_idx = hw_irq % dgc->irqs_per_chip; |
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clear_bit(irq_idx, &gc->installed); |
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irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL, |
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NULL); |
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} |
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struct irq_domain_ops irq_generic_chip_ops = { |
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.map = irq_map_generic_chip, |
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.unmap = irq_unmap_generic_chip, |
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.xlate = irq_domain_xlate_onetwocell, |
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}; |
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EXPORT_SYMBOL_GPL(irq_generic_chip_ops); |
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/** |
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* irq_setup_generic_chip - Setup a range of interrupts with a generic chip |
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* @gc: Generic irq chip holding all data |
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* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base |
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* @flags: Flags for initialization |
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* @clr: IRQ_* bits to clear |
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* @set: IRQ_* bits to set |
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* |
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* Set up max. 32 interrupts starting from gc->irq_base. Note, this |
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* initializes all interrupts to the primary irq_chip_type and its |
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* associated handler. |
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*/ |
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void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk, |
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enum irq_gc_flags flags, unsigned int clr, |
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unsigned int set) |
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{ |
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struct irq_chip_type *ct = gc->chip_types; |
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struct irq_chip *chip = &ct->chip; |
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unsigned int i; |
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raw_spin_lock(&gc_lock); |
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list_add_tail(&gc->list, &gc_list); |
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raw_spin_unlock(&gc_lock); |
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irq_gc_init_mask_cache(gc, flags); |
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for (i = gc->irq_base; msk; msk >>= 1, i++) { |
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if (!(msk & 0x01)) |
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continue; |
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if (flags & IRQ_GC_INIT_NESTED_LOCK) |
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irq_set_lockdep_class(i, &irq_nested_lock_class, |
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&irq_nested_request_class); |
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if (!(flags & IRQ_GC_NO_MASK)) { |
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struct irq_data *d = irq_get_irq_data(i); |
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if (chip->irq_calc_mask) |
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chip->irq_calc_mask(d); |
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else |
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d->mask = 1 << (i - gc->irq_base); |
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} |
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irq_set_chip_and_handler(i, chip, ct->handler); |
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irq_set_chip_data(i, gc); |
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irq_modify_status(i, clr, set); |
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} |
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gc->irq_cnt = i - gc->irq_base; |
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} |
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EXPORT_SYMBOL_GPL(irq_setup_generic_chip); |
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/** |
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* irq_setup_alt_chip - Switch to alternative chip |
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* @d: irq_data for this interrupt |
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* @type: Flow type to be initialized |
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* |
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* Only to be called from chip->irq_set_type() callbacks. |
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*/ |
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int irq_setup_alt_chip(struct irq_data *d, unsigned int type) |
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{ |
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); |
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struct irq_chip_type *ct = gc->chip_types; |
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unsigned int i; |
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for (i = 0; i < gc->num_ct; i++, ct++) { |
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if (ct->type & type) { |
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d->chip = &ct->chip; |
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irq_data_to_desc(d)->handle_irq = ct->handler; |
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return 0; |
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} |
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} |
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return -EINVAL; |
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} |
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EXPORT_SYMBOL_GPL(irq_setup_alt_chip); |
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/** |
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* irq_remove_generic_chip - Remove a chip |
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* @gc: Generic irq chip holding all data |
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* @msk: Bitmask holding the irqs to initialize relative to gc->irq_base |
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* @clr: IRQ_* bits to clear |
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* @set: IRQ_* bits to set |
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* |
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* Remove up to 32 interrupts starting from gc->irq_base. |
|
*/ |
|
void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk, |
|
unsigned int clr, unsigned int set) |
|
{ |
|
unsigned int i = gc->irq_base; |
|
|
|
raw_spin_lock(&gc_lock); |
|
list_del(&gc->list); |
|
raw_spin_unlock(&gc_lock); |
|
|
|
for (; msk; msk >>= 1, i++) { |
|
if (!(msk & 0x01)) |
|
continue; |
|
|
|
/* Remove handler first. That will mask the irq line */ |
|
irq_set_handler(i, NULL); |
|
irq_set_chip(i, &no_irq_chip); |
|
irq_set_chip_data(i, NULL); |
|
irq_modify_status(i, clr, set); |
|
} |
|
} |
|
EXPORT_SYMBOL_GPL(irq_remove_generic_chip); |
|
|
|
static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc) |
|
{ |
|
unsigned int virq; |
|
|
|
if (!gc->domain) |
|
return irq_get_irq_data(gc->irq_base); |
|
|
|
/* |
|
* We don't know which of the irqs has been actually |
|
* installed. Use the first one. |
|
*/ |
|
if (!gc->installed) |
|
return NULL; |
|
|
|
virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed)); |
|
return virq ? irq_get_irq_data(virq) : NULL; |
|
} |
|
|
|
#ifdef CONFIG_PM |
|
static int irq_gc_suspend(void) |
|
{ |
|
struct irq_chip_generic *gc; |
|
|
|
list_for_each_entry(gc, &gc_list, list) { |
|
struct irq_chip_type *ct = gc->chip_types; |
|
|
|
if (ct->chip.irq_suspend) { |
|
struct irq_data *data = irq_gc_get_irq_data(gc); |
|
|
|
if (data) |
|
ct->chip.irq_suspend(data); |
|
} |
|
|
|
if (gc->suspend) |
|
gc->suspend(gc); |
|
} |
|
return 0; |
|
} |
|
|
|
static void irq_gc_resume(void) |
|
{ |
|
struct irq_chip_generic *gc; |
|
|
|
list_for_each_entry(gc, &gc_list, list) { |
|
struct irq_chip_type *ct = gc->chip_types; |
|
|
|
if (gc->resume) |
|
gc->resume(gc); |
|
|
|
if (ct->chip.irq_resume) { |
|
struct irq_data *data = irq_gc_get_irq_data(gc); |
|
|
|
if (data) |
|
ct->chip.irq_resume(data); |
|
} |
|
} |
|
} |
|
#else |
|
#define irq_gc_suspend NULL |
|
#define irq_gc_resume NULL |
|
#endif |
|
|
|
static void irq_gc_shutdown(void) |
|
{ |
|
struct irq_chip_generic *gc; |
|
|
|
list_for_each_entry(gc, &gc_list, list) { |
|
struct irq_chip_type *ct = gc->chip_types; |
|
|
|
if (ct->chip.irq_pm_shutdown) { |
|
struct irq_data *data = irq_gc_get_irq_data(gc); |
|
|
|
if (data) |
|
ct->chip.irq_pm_shutdown(data); |
|
} |
|
} |
|
} |
|
|
|
static struct syscore_ops irq_gc_syscore_ops = { |
|
.suspend = irq_gc_suspend, |
|
.resume = irq_gc_resume, |
|
.shutdown = irq_gc_shutdown, |
|
}; |
|
|
|
static int __init irq_gc_init_ops(void) |
|
{ |
|
register_syscore_ops(&irq_gc_syscore_ops); |
|
return 0; |
|
} |
|
device_initcall(irq_gc_init_ops);
|
|
|