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46 lines
1.3 KiB
46 lines
1.3 KiB
/* SPDX-License-Identifier: GPL-2.0 */ |
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#ifndef _TOOLS_LINUX_ASM_X86_BARRIER_H |
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#define _TOOLS_LINUX_ASM_X86_BARRIER_H |
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/* |
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* Copied from the Linux kernel sources, and also moving code |
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* out from tools/perf/perf-sys.h so as to make it be located |
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* in a place similar as in the kernel sources. |
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* |
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* Force strict CPU ordering. |
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* And yes, this is required on UP too when we're talking |
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* to devices. |
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*/ |
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#if defined(__i386__) |
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/* |
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* Some non-Intel clones support out of order store. wmb() ceases to be a |
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* nop for these. |
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*/ |
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#define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") |
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#define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") |
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#define wmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") |
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#elif defined(__x86_64__) |
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#define mb() asm volatile("mfence" ::: "memory") |
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#define rmb() asm volatile("lfence" ::: "memory") |
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#define wmb() asm volatile("sfence" ::: "memory") |
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#define smp_rmb() barrier() |
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#define smp_wmb() barrier() |
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#define smp_mb() asm volatile("lock; addl $0,-132(%%rsp)" ::: "memory", "cc") |
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#endif |
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#if defined(__x86_64__) |
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#define smp_store_release(p, v) \ |
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do { \ |
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barrier(); \ |
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WRITE_ONCE(*p, v); \ |
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} while (0) |
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#define smp_load_acquire(p) \ |
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({ \ |
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typeof(*p) ___p1 = READ_ONCE(*p); \ |
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barrier(); \ |
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___p1; \ |
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}) |
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#endif /* defined(__x86_64__) */ |
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#endif /* _TOOLS_LINUX_ASM_X86_BARRIER_H */
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