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115 lines
3.7 KiB
115 lines
3.7 KiB
Samsung Exynos SoC USB controller |
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The USB devices interface with USB controllers on Exynos SOCs. |
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The device node has following properties. |
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EHCI |
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Required properties: |
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- compatible: should be "samsung,exynos4210-ehci" for USB 2.0 |
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EHCI controller in host mode. |
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- reg: physical base address of the controller and length of memory mapped |
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region. |
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- interrupts: interrupt number to the cpu. |
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- clocks: from common clock binding: handle to usb clock. |
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- clock-names: from common clock binding: Shall be "usbhost". |
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- phys: from the *Generic PHY* bindings; array specifying phy(s) used |
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by the root port. |
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- phy-names: from the *Generic PHY* bindings; array of the names for |
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each phy for the root ports, must be a subset of the following: |
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"host", "hsic0", "hsic1". |
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Optional properties: |
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- samsung,vbus-gpio: if present, specifies the GPIO that |
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needs to be pulled up for the bus to be powered. |
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Example: |
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usb@12110000 { |
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compatible = "samsung,exynos4210-ehci"; |
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reg = <0x12110000 0x100>; |
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interrupts = <0 71 0>; |
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samsung,vbus-gpio = <&gpx2 6 1 3 3>; |
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clocks = <&clock 285>; |
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clock-names = "usbhost"; |
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phys = <&usb2phy 1>; |
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phy-names = "host"; |
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}; |
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OHCI |
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Required properties: |
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- compatible: should be "samsung,exynos4210-ohci" for USB 2.0 |
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OHCI companion controller in host mode. |
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- reg: physical base address of the controller and length of memory mapped |
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region. |
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- interrupts: interrupt number to the cpu. |
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- clocks: from common clock binding: handle to usb clock. |
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- clock-names: from common clock binding: Shall be "usbhost". |
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- phys: from the *Generic PHY* bindings; array specifying phy(s) used |
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by the root port. |
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- phy-names: from the *Generic PHY* bindings; array of the names for |
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each phy for the root ports, must be a subset of the following: |
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"host", "hsic0", "hsic1". |
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Example: |
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usb@12120000 { |
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compatible = "samsung,exynos4210-ohci"; |
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reg = <0x12120000 0x100>; |
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interrupts = <0 71 0>; |
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clocks = <&clock 285>; |
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clock-names = "usbhost"; |
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phys = <&usb2phy 1>; |
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phy-names = "host"; |
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}; |
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DWC3 |
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Required properties: |
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- compatible: should be one of the following - |
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"samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on |
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Exynos5250/5420. |
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"samsung,exynos5433-dwusb3": for USB 3.0 DWC3 controller on |
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Exynos5433. |
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"samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7. |
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- #address-cells, #size-cells : should be '1' if the device has sub-nodes |
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with 'reg' property. |
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- ranges: allows valid 1:1 translation between child's address space and |
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parent's address space |
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- clocks: Clock IDs array as required by the controller. |
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- clock-names: Names of clocks corresponding to IDs in the clock property. |
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Following clock names shall be provided for different |
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compatibles: |
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- samsung,exynos5250-dwusb3: "usbdrd30", |
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- samsung,exynos5433-dwusb3: "aclk", "susp_clk", "pipe_pclk", |
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"phyclk", |
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- samsung,exynos7-dwusb3: "usbdrd30", "usbdrd30_susp_clk", |
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"usbdrd30_axius_clk" |
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- vdd10-supply: 1.0V powr supply |
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- vdd33-supply: 3.0V/3.3V power supply |
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Sub-nodes: |
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The dwc3 core should be added as subnode to Exynos dwc3 glue. |
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- dwc3 : |
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The binding details of dwc3 can be found in: |
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Documentation/devicetree/bindings/usb/snps,dwc3.yaml |
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Example: |
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usb@12000000 { |
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compatible = "samsung,exynos5250-dwusb3"; |
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clocks = <&clock 286>; |
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clock-names = "usbdrd30"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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ranges; |
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vdd10-supply = <&ldo11_reg>; |
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vdd33-supply = <&ldo9_reg>; |
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dwc3 { |
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compatible = "synopsys,dwc3"; |
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reg = <0x12000000 0x10000>; |
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interrupts = <0 72 0>; |
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usb-phy = <&usb2_phy &usb3_phy>; |
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}; |
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};
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