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32 lines
1.2 KiB
32 lines
1.2 KiB
* Cadence Universal Flash Storage (UFS) Controller |
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UFS nodes are defined to describe on-chip UFS host controllers. |
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Each UFS controller instance should have its own node. |
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Please see the ufshcd-pltfrm.txt for a list of all available properties. |
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Required properties: |
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- compatible : Compatible list, contains one of the following controllers: |
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"cdns,ufshc" - Generic CDNS HCI, |
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"cdns,ufshc-m31-16nm" - CDNS UFS HC + M31 16nm PHY |
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complemented with the JEDEC version: |
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"jedec,ufs-2.0" |
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- reg : Address and length of the UFS register set. |
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- interrupts : One interrupt mapping. |
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- freq-table-hz : Clock frequency table. |
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See the ufshcd-pltfrm.txt for details. |
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- clocks : List of phandle and clock specifier pairs. |
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- clock-names : List of clock input name strings sorted in the same |
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order as the clocks property. "core_clk" is mandatory. |
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Depending on a type of a PHY, |
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the "phy_clk" clock can also be added, if needed. |
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Example: |
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ufs@fd030000 { |
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compatible = "cdns,ufshc", "jedec,ufs-2.0"; |
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reg = <0xfd030000 0x10000>; |
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interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>; |
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freq-table-hz = <0 0>, <0 0>; |
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clocks = <&ufs_core_clk>, <&ufs_phy_clk>; |
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clock-names = "core_clk", "phy_clk"; |
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};
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