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51 lines
1.1 KiB
51 lines
1.1 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/spi/spi-zynqmp-qspi.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Xilinx Zynq UltraScale+ MPSoC GQSPI controller Device Tree Bindings |
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maintainers: |
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- Michal Simek <[email protected]> |
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allOf: |
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- $ref: "spi-controller.yaml#" |
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properties: |
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compatible: |
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const: xlnx,zynqmp-qspi-1.0 |
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reg: |
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maxItems: 2 |
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interrupts: |
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maxItems: 1 |
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clock-names: |
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items: |
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- const: ref_clk |
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- const: pclk |
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clocks: |
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maxItems: 2 |
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unevaluatedProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/xlnx-zynqmp-clk.h> |
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soc { |
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#address-cells = <2>; |
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#size-cells = <2>; |
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qspi: spi@ff0f0000 { |
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compatible = "xlnx,zynqmp-qspi-1.0"; |
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clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>; |
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clock-names = "ref_clk", "pclk"; |
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interrupts = <0 15 4>; |
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interrupt-parent = <&gic>; |
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reg = <0x0 0xff0f0000 0x0 0x1000>, |
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<0x0 0xc0000000 0x0 0x8000000>; |
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}; |
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};
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