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65 lines
2.0 KiB
65 lines
2.0 KiB
ARM Freescale DSPI controller |
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Required properties: |
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- compatible : must be one of: |
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"fsl,vf610-dspi", |
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"fsl,ls1021a-v1.0-dspi", |
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"fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), |
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"fsl,ls1028a-dspi", |
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"fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), |
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"fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), |
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"fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"), |
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"fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"), |
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"fsl,ls2085a-dspi", |
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"fsl,lx2160a-dspi", |
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- reg : Offset and length of the register set for the device |
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- interrupts : Should contain SPI controller interrupt |
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- clocks: from common clock binding: handle to dspi clock. |
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- clock-names: from common clock binding: Shall be "dspi". |
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- pinctrl-0: pin control group to be used for this controller. |
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- pinctrl-names: must contain a "default" entry. |
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- spi-num-chipselects : the number of the chipselect signals. |
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Optional property: |
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- big-endian: If present the dspi device's registers are implemented |
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in big endian mode. |
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- bus-num : the slave chip chipselect signal number. |
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Optional SPI slave node properties: |
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- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip |
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select and the start of clock signal, at the start of a transfer. |
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- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock |
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signal and deactivating chip select, at the end of a transfer. |
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Example: |
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dspi0@4002c000 { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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compatible = "fsl,vf610-dspi"; |
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reg = <0x4002c000 0x1000>; |
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interrupts = <0 67 0x04>; |
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clocks = <&clks VF610_CLK_DSPI0>; |
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clock-names = "dspi"; |
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spi-num-chipselects = <5>; |
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bus-num = <0>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_dspi0_1>; |
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big-endian; |
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sflash: at26df081a@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "atmel,at26df081a"; |
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spi-max-frequency = <16000000>; |
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spi-cpol; |
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spi-cpha; |
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reg = <0>; |
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linux,modalias = "m25p80"; |
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modal = "at26df081a"; |
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fsl,spi-cs-sck-delay = <100>; |
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fsl,spi-sck-cs-delay = <50>; |
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}; |
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}; |
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