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91 lines
2.0 KiB
91 lines
2.0 KiB
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
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%YAML 1.2 |
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--- |
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$id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml# |
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$schema: http://devicetree.org/meta-schemas/core.yaml# |
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title: Rockchip Serial Flash Controller (SFC) |
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maintainers: |
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- Heiko Stuebner <[email protected]> |
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- Chris Morgan <[email protected]> |
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allOf: |
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- $ref: spi-controller.yaml# |
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properties: |
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compatible: |
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const: rockchip,sfc |
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description: |
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The rockchip sfc controller is a standalone IP with version register, |
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and the driver can handle all the feature difference inside the IP |
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depending on the version register. |
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reg: |
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maxItems: 1 |
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interrupts: |
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maxItems: 1 |
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clocks: |
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items: |
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- description: Bus Clock |
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- description: Module Clock |
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clock-names: |
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items: |
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- const: clk_sfc |
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- const: hclk_sfc |
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power-domains: |
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maxItems: 1 |
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rockchip,sfc-no-dma: |
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description: Disable DMA and utilize FIFO mode only |
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type: boolean |
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patternProperties: |
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"^flash@[0-3]$": |
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type: object |
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properties: |
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reg: |
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minimum: 0 |
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maximum: 3 |
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required: |
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- compatible |
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- reg |
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- interrupts |
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- clocks |
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- clock-names |
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unevaluatedProperties: false |
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examples: |
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- | |
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#include <dt-bindings/clock/px30-cru.h> |
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#include <dt-bindings/interrupt-controller/arm-gic.h> |
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#include <dt-bindings/power/px30-power.h> |
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sfc: spi@ff3a0000 { |
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compatible = "rockchip,sfc"; |
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reg = <0xff3a0000 0x4000>; |
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; |
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clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; |
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clock-names = "clk_sfc", "hclk_sfc"; |
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pinctrl-0 = <&sfc_clk &sfc_cs &sfc_bus2>; |
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pinctrl-names = "default"; |
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power-domains = <&power PX30_PD_MMC_NAND>; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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flash@0 { |
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compatible = "jedec,spi-nor"; |
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reg = <0>; |
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spi-max-frequency = <108000000>; |
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spi-rx-bus-width = <2>; |
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spi-tx-bus-width = <2>; |
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}; |
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}; |
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...
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