forked from Qortal/Brooklyn
You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
35 lines
1.3 KiB
35 lines
1.3 KiB
Nuvoton NPCM Peripheral Serial Peripheral Interface(PSPI) controller driver |
|
|
|
Nuvoton NPCM7xx SOC support two PSPI channels. |
|
|
|
Required properties: |
|
- compatible : "nuvoton,npcm750-pspi" for NPCM7XX BMC |
|
- #address-cells : should be 1. see spi-bus.txt |
|
- #size-cells : should be 0. see spi-bus.txt |
|
- specifies physical base address and size of the register. |
|
- interrupts : contain PSPI interrupt. |
|
- clocks : phandle of PSPI reference clock. |
|
- clock-names: Should be "clk_apb5". |
|
- pinctrl-names : a pinctrl state named "default" must be defined. |
|
- pinctrl-0 : phandle referencing pin configuration of the device. |
|
- resets : phandle to the reset control for this device. |
|
- cs-gpios: Specifies the gpio pins to be used for chipselects. |
|
See: Documentation/devicetree/bindings/spi/spi-bus.txt |
|
|
|
Optional properties: |
|
- clock-frequency : Input clock frequency to the PSPI block in Hz. |
|
Default is 25000000 Hz. |
|
|
|
spi0: spi@f0200000 { |
|
compatible = "nuvoton,npcm750-pspi"; |
|
reg = <0xf0200000 0x1000>; |
|
pinctrl-names = "default"; |
|
pinctrl-0 = <&pspi1_pins>; |
|
#address-cells = <1>; |
|
#size-cells = <0>; |
|
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
|
clocks = <&clk NPCM7XX_CLK_APB5>; |
|
clock-names = "clk_apb5"; |
|
resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1> |
|
cs-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; |
|
};
|
|
|