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40 lines
1.4 KiB
40 lines
1.4 KiB
Spreadtrum PWM controller |
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Spreadtrum SoCs PWM controller provides 4 PWM channels. |
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Required properties: |
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- compatible : Should be "sprd,ums512-pwm". |
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- reg: Physical base address and length of the controller's registers. |
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- clocks: The phandle and specifier referencing the controller's clocks. |
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- clock-names: Should contain following entries: |
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"pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3). |
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"enablen": for PWM channel n enable clock (n range: 0 ~ 3). |
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- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of |
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the cells format. |
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Optional properties: |
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- assigned-clocks: Reference to the PWM clock entries. |
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- assigned-clock-parents: The phandle of the parent clock of PWM clock. |
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Example: |
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pwms: pwm@32260000 { |
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compatible = "sprd,ums512-pwm"; |
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reg = <0 0x32260000 0 0x10000>; |
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clock-names = "pwm0", "enable0", |
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"pwm1", "enable1", |
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"pwm2", "enable2", |
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"pwm3", "enable3"; |
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clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>, |
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<&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>, |
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<&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>, |
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<&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>; |
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assigned-clocks = <&aon_clk CLK_PWM0>, |
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<&aon_clk CLK_PWM1>, |
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<&aon_clk CLK_PWM2>, |
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<&aon_clk CLK_PWM3>; |
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assigned-clock-parents = <&ext_26m>, |
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<&ext_26m>, |
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<&ext_26m>, |
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<&ext_26m>; |
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#pwm-cells = <2>; |
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};
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