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20 lines
559 B
20 lines
559 B
* Freescale PQ3 and QorIQ based Cache SRAM |
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Freescale's mpc85xx and some QorIQ platforms provide an |
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option of configuring a part of (or full) cache memory |
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as SRAM. This cache SRAM representation in the device |
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tree should be done as under:- |
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Required properties: |
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- compatible : should be "fsl,p2020-cache-sram" |
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- fsl,cache-sram-ctlr-handle : points to the L2 controller |
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- reg : offset and length of the cache-sram. |
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Example: |
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cache-sram@fff00000 { |
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fsl,cache-sram-ctlr-handle = <&L2>; |
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reg = <0 0xfff00000 0 0x10000>; |
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compatible = "fsl,p2020-cache-sram"; |
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};
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