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176 lines
5.5 KiB
176 lines
5.5 KiB
Qualcomm SDM845 TLMM block |
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This binding describes the Top Level Mode Multiplexer block found in the |
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SDM845 platform. |
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- compatible: |
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Usage: required |
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Value type: <string> |
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Definition: must be "qcom,sdm845-pinctrl" |
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- reg: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: the base address and size of the TLMM register space. |
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- interrupts: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: should specify the TLMM summary IRQ. |
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- interrupt-controller: |
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Usage: required |
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Value type: <none> |
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Definition: identifies this node as an interrupt controller |
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- #interrupt-cells: |
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Usage: required |
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Value type: <u32> |
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Definition: must be 2. Specifying the pin number and flags, as defined |
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in <dt-bindings/interrupt-controller/irq.h> |
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- gpio-controller: |
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Usage: required |
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Value type: <none> |
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Definition: identifies this node as a gpio controller |
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- #gpio-cells: |
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Usage: required |
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Value type: <u32> |
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Definition: must be 2. Specifying the pin number and flags, as defined |
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in <dt-bindings/gpio/gpio.h> |
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for |
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a general description of GPIO and interrupt bindings. |
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Please refer to pinctrl-bindings.txt in this directory for details of the |
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common pinctrl bindings used by client devices, including the meaning of the |
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phrase "pin configuration node". |
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The pin configuration nodes act as a container for an arbitrary number of |
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subnodes. Each of these subnodes represents some desired configuration for a |
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pin, a group, or a list of pins or groups. This configuration can include the |
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mux function to select on those pin(s)/group(s), and various pin configuration |
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parameters, such as pull-up, drive strength, etc. |
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PIN CONFIGURATION NODES: |
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The name of each subnode is not important; all subnodes should be enumerated |
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and processed purely based on their content. |
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Each subnode only affects those parameters that are explicitly listed. In |
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other words, a subnode that lists a mux function but no pin configuration |
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parameters implies no information about any pin configuration parameters. |
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Similarly, a pin subnode that describes a pullup parameter implies no |
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information about e.g. the mux function. |
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The following generic properties as defined in pinctrl-bindings.txt are valid |
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to specify in a pin configuration subnode: |
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- pins: |
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Usage: required |
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Value type: <string-array> |
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Definition: List of gpio pins affected by the properties specified in |
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this subnode. |
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Valid pins are: |
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gpio0-gpio149 |
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Supports mux, bias and drive-strength |
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sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset |
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Supports bias and drive-strength |
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- function: |
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Usage: required |
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Value type: <string> |
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Definition: Specify the alternative function to be configured for the |
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specified pins. Functions are only valid for gpio pins. |
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Valid values are: |
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gpio, adsp_ext, agera_pll, atest_char, atest_tsens, |
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atest_tsens2, atest_usb1, atest_usb10, atest_usb11, |
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atest_usb12, atest_usb13, atest_usb2, atest_usb20, |
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atest_usb21, atest_usb22, atest_usb23, audio_ref, |
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btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0, |
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cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng, |
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cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, |
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ddr_pxi1, ddr_pxi2, ddr_pxi3, edp_hot, edp_lcd, gcc_gp1, |
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gcc_gp2, gcc_gp3, jitter_bist, ldo_en, ldo_update, |
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lpass_slimbus, m_voc, mdp_vsync, mdp_vsync0, mdp_vsync1, |
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mdp_vsync2, mdp_vsync3, mss_lte, nav_pps, pa_indicator, |
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pci_e0, pci_e1, phase_flag, pll_bist, pll_bypassnl, |
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pll_reset, pri_mi2s, pri_mi2s_ws, prng_rosc, qdss_cti, |
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qdss, qlink_enable, qlink_request, qua_mi2s, qup0, qup1, |
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qup10, qup11, qup12, qup13, qup14, qup15, qup2, qup3, qup4, |
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qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, |
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qspi_clk, qspi_cs, qspi_data, sd_write, sdc4_clk, sdc4_cmd, |
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sdc4_data, sec_mi2s, sp_cmu, spkr_i2s, ter_mi2s, tgu_ch0, |
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tgu_ch1, tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, |
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tsif1_clk, tsif1_data, tsif1_en, tsif1_error, tsif1_sync, |
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tsif2_clk, tsif2_data, tsif2_en, tsif2_error, tsif2_sync, |
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uim1_clk, uim1_data, uim1_present, uim1_reset, uim2_clk, |
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uim2_data, uim2_present, uim2_reset, uim_batt, usb_phy, |
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vfr_1, vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0, |
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wlan2_adc1, |
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- bias-disable: |
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Usage: optional |
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Value type: <none> |
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Definition: The specified pins should be configured as no pull. |
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- bias-pull-down: |
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Usage: optional |
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Value type: <none> |
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Definition: The specified pins should be configured as pull down. |
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- bias-pull-up: |
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Usage: optional |
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Value type: <none> |
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Definition: The specified pins should be configured as pull up. |
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- output-high: |
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Usage: optional |
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Value type: <none> |
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Definition: The specified pins are configured in output mode, driven |
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high. |
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Not valid for sdc pins. |
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- output-low: |
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Usage: optional |
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Value type: <none> |
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Definition: The specified pins are configured in output mode, driven |
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low. |
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Not valid for sdc pins. |
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- drive-strength: |
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Usage: optional |
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Value type: <u32> |
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Definition: Selects the drive strength for the specified pins, in mA. |
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Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 |
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Example: |
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tlmm: pinctrl@3400000 { |
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compatible = "qcom,sdm845-pinctrl"; |
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reg = <0x03400000 0xc00000>; |
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interrupts = <GIC_SPI 208 0>; |
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gpio-controller; |
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#gpio-cells = <2>; |
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interrupt-controller; |
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#interrupt-cells = <2>; |
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qup9_active: qup9-active { |
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mux { |
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pins = "gpio4", "gpio5"; |
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function = "qup9"; |
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}; |
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config { |
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pins = "gpio4", "gpio5"; |
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drive-strength = <2>; |
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bias-disable; |
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}; |
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}; |
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};
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