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132 lines
5.1 KiB
132 lines
5.1 KiB
* Mediatek MT8183 Pin Controller |
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The Mediatek's Pin controller is used to control SoC pins. |
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Required properties: |
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- compatible: value should be one of the following. |
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"mediatek,mt8183-pinctrl", compatible with mt8183 pinctrl. |
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- gpio-controller : Marks the device node as a gpio controller. |
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- #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO |
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binding is used, the amount of cells must be specified as 2. See the below |
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mentioned gpio binding representation for description of particular cells. |
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- gpio-ranges : gpio valid number range. |
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- reg: physical address base for gpio base registers. There are 10 GPIO |
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physical address base in mt8183. |
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Optional properties: |
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- reg-names: gpio base register names. There are 10 gpio base register |
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names in mt8183. They are "iocfg0", "iocfg1", "iocfg2", "iocfg3", "iocfg4", |
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"iocfg5", "iocfg6", "iocfg7", "iocfg8", "eint". |
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- interrupt-controller: Marks the device node as an interrupt controller |
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- #interrupt-cells: Should be two. |
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- interrupts : The interrupt outputs to sysirq. |
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Please refer to pinctrl-bindings.txt in this directory for details of the |
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common pinctrl bindings used by client devices. |
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Subnode format |
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A pinctrl node should contain at least one subnodes representing the |
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pinctrl groups available on the machine. Each subnode will list the |
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pins it needs, and how they should be configured, with regard to muxer |
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configuration, pullups, drive strength, input enable/disable and input schmitt. |
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node { |
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pinmux = <PIN_NUMBER_PINMUX>; |
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GENERIC_PINCONFIG; |
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}; |
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Required properties: |
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- pinmux: integer array, represents gpio pin number and mux setting. |
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Supported pin number and mux varies for different SoCs, and are defined |
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as macros in boot/dts/<soc>-pinfunc.h directly. |
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Optional properties: |
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- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable, |
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bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, |
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output-high, input-schmitt-enable, input-schmitt-disable |
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and drive-strength are valid. |
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Some special pins have extra pull up strength, there are R0 and R1 pull-up |
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resistors available, but for user, it's only need to set R1R0 as 00, 01, |
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10 or 11. So It needs config "mediatek,pull-up-adv" or |
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"mediatek,pull-down-adv" to support arguments for those special pins. |
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Valid arguments are from 0 to 3. |
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mediatek,tdsel: An integer describing the steps for output level shifter |
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duty cycle when asserted (high pulse width adjustment). Valid arguments |
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are from 0 to 15. |
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mediatek,rdsel: An integer describing the steps for input level shifter |
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duty cycle when asserted (high pulse width adjustment). Valid arguments |
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are from 0 to 63. |
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When config drive-strength, it can support some arguments, such as |
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MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h. |
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It can only support 2/4/6/8/10/12/14/16mA in mt8183. |
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For I2C pins, there are existing generic driving setup and the specific |
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driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA driving |
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adjustment in generic driving setup. But in specific driving setup, |
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they can support 0.125/0.25/0.5/1mA adjustment. If we enable specific |
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driving setup for I2C pins, the existing generic driving setup will be |
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disabled. For some special features, we need the I2C pins specific |
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driving setup. The specific driving setup is controlled by E1E0EN. |
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So we need add extra vendor driving preperty instead of |
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the generic driving property. |
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We can add "mediatek,drive-strength-adv = <XXX>;" to describe the specific |
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driving setup property. "XXX" means the value of E1E0EN. EN is 0 or 1. |
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It is used to enable or disable the specific driving setup. |
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E1E0 is used to describe the detail strength specification of the I2C pin. |
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When E1=0/E0=0, the strength is 0.125mA. |
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When E1=0/E0=1, the strength is 0.25mA. |
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When E1=1/E0=0, the strength is 0.5mA. |
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When E1=1/E0=1, the strength is 1mA. |
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So the valid arguments of "mediatek,drive-strength-adv" are from 0 to 7. |
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Examples: |
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#include "mt8183-pinfunc.h" |
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... |
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{ |
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pio: pinctrl@10005000 { |
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compatible = "mediatek,mt8183-pinctrl"; |
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reg = <0 0x10005000 0 0x1000>, |
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<0 0x11f20000 0 0x1000>, |
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<0 0x11e80000 0 0x1000>, |
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<0 0x11e70000 0 0x1000>, |
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<0 0x11e90000 0 0x1000>, |
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<0 0x11d30000 0 0x1000>, |
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<0 0x11d20000 0 0x1000>, |
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<0 0x11c50000 0 0x1000>, |
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<0 0x11f30000 0 0x1000>, |
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<0 0x1000b000 0 0x1000>; |
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reg-names = "iocfg0", "iocfg1", "iocfg2", |
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"iocfg3", "iocfg4", "iocfg5", |
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"iocfg6", "iocfg7", "iocfg8", |
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"eint"; |
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gpio-controller; |
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#gpio-cells = <2>; |
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gpio-ranges = <&pio 0 0 192>; |
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interrupt-controller; |
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interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; |
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#interrupt-cells = <2>; |
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i2c0_pins_a: i2c0 { |
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pins1 { |
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pinmux = <PINMUX_GPIO48__FUNC_SCL5>, |
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<PINMUX_GPIO49__FUNC_SDA5>; |
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mediatek,pull-up-adv = <3>; |
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mediatek,drive-strength-adv = <7>; |
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}; |
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}; |
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i2c1_pins_a: i2c1 { |
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pins { |
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pinmux = <PINMUX_GPIO50__FUNC_SCL3>, |
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<PINMUX_GPIO51__FUNC_SDA3>; |
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mediatek,pull-down-adv = <2>; |
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mediatek,drive-strength-adv = <4>; |
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}; |
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}; |
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... |
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}; |
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};
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